Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow

Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker

WILSONVILLE, Ore., January 14, 2008 - Mentor Graphics Corporation today announced the availability of a new electronic system level (ESL) hardware design and verfication flow featuring Mentor's Catapult® C Synthesis tool and Calypto Design Systems' SLEC sequential equivalence checker. Proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct. These customer results validate the Mentor/Calypto design flow, and indicate its readiness for broad production usage by companies using ESL methodologies for hardware design.

These two best-in-class design tools offer a superior, integrated solution for ANSI C++ synthesis and verification. The Catapult C Synthesis tool enables hardware designers to create optimized RTL descriptions 10-100x faster than manual design methods. Calypto's SLEC comprehensively verifies that RTL designs are functionally equivalent to system-level models without testbenches or assertions. SLEC uses sequential analysis techniques to verify Catapult C's RTL output functionally matches the original ANSI C++ source. The integration of the Catapult C Synthesis tool and SLEC increases designer productivity by providing users with a fast, exhaustive, vector-less design and verification methodology.

"With high-level synthesis tools, it is essential to verify that the high-level C description is functionally the same at the tool's RTL output," said Mr. Haruhisa Kashiwagi, Senior Manager, System Level Design Group, Development-2 of STARC. "During STARC's ASUKA II project, we evaluated the Catapult C Synthesis/SLEC flow from Mentor Graphics and Calypto Design Systems. Using several examples, we have verified that the RTL generated from the Catapult C Synthesis tool has the same functionality as the high-level source code. We were able to accomplish this in a short period of time, and we ascertained a seamless integration between the two tools. We think this is a very valuable flow for companies interested in ESL methods for hardware design."

With this integration, the Catapult C Synthesis tool users can automatically generate RTL from a pure ANSI C++ description, and then create the setup scripts to launch the SLEC verification environment. This allows users to verify equivalence between the pure ANSI C++ and RTL descriptions quickly as well as verify additional design optimizations before handoff for final integrated circuit implementation.

"Customer experience with the SLEC/Catapult C flow confirms that ESL synthesis and verification is ready for mainstream design," said Tom Sandoval, chief executive officer Calypto Design Systems. "STARC's project demonstrates the interoperability and productivity benefits of using an ESL flow for large-scale hardware design."

"For complex designs, system-level synthesis and verification provide efficiencies that reduce design time and increase overall profitability. STARC's recent evaluation has proven that the Mentor/Calypto solution delivers a substantial productivity advantage, giving users relief from the competing forces of increasing design complexity and time-to-market pressure," said Simon Bloch, general manager, Design Creation and Synthesis Division, Mentor Graphics Corp. "We praise STARC for validating our integrated ESL tool flow for the benefit of its member companies."

About Calypto
Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. It delivers software products to leading edge semiconductor and systems companies worldwide. Calypto is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Email: More information about Calypto may be found at:

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $825 million and employs approximately 4,300 people worldwide.

Corporate headquarters are located at
8005 S.W. Boeckman Road
Oregon 97070-7777.
World Wide Web site:

For more information, please contact:
Larry Toda
Mentor Graphics

Ry Schwark
Mentor Graphics

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