LAN PHY and PHY/SerDes Devices come in pin compatible form.
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Press Release Summary:
Puma AEL1004 WIS-enabled 10GbE PHY/SerDes device incorporates on-board clock synthesizers that eliminate need for 2 clock sources for Ethernet and SONET/SDH rates; single clock input of 155.52 MHz drives SONET/SDH and Ethernet/XAUI clocking requirements. Puma AEL1006 LAN PHY device integrates VCSEL driver functionality as well as on-board clock synthesizer functionality, allowing Ethernet/XAUI rates to be synthesized from 50 MHz input.
Original Press Release:
Aeluros Integrates New Features into Industry's Lowest-Power 10 Gbps PHY/SerDes
Integrated Clocking Synthesizers and VCSEL Driver Functionality Adds to Industry-Leading Performance
MOUNTAIN VIEW, Calif., Jan. 30 / -- Aeluros, the leading supplier of low-power CMOS based 10G PHY solutions, today announced the immediate availability of its next generation 10GbE PHY/SerDes devices with integrated clock synthesizers and VCSEL driver functionality. With the availability of these devices -- in pin compatible form -- Aeluros has added to its industry leading 800mW Puma AEL1001/AEL1002 device family, providing a complete portfolio of 10 Gbps-to-XAUI devices for optical module and line card applications.
The Puma AEL1004, a WIS-enabled version of the Puma product family of 10GbE PHY/SerDes devices, incorporates on-board clock synthesizers that eliminate the need for board designers to provide two clock sources for Ethernet and SONET/SDH rates. With this patent-pending design approach, a single clock input of 155.52MHz is sufficient to drive both the SONET/SDH and Ethernet/XAUI clocking requirements in the device. Additionally, on-board clean-up circuitry also allows the device to provide stratum-3 level line-timing capability for SONET/SDH timing requirements.
The Puma AEL1006 device is a next generation LAN PHY device with integrated VCSEL driver functionality. Reference hardware that demonstrates this functionality in X2 optical modules is also available. This device also includes on-board clock synthesizer functionality that allows Ethernet/XAUI rates to be synthesized from a low-cost 50 MHz input -- allowing further cost reduction of the optical modules.
"The continued integration of additional functionality -- as shown in the Puma AEL 100x device family from Aeluros -- reduces the number of required components per optical module which ultimately results in lower costs," said Steve Joiner, Technical Manager at Finisar, Corp. "Additionally, the low power consumption of the Aeluros 10G PHY device family is a very important parameter for new optical modules with restrictive power requirements."
"By integrating additional functionality into our industry-leading low power 10GbE PHY device family, we have demonstrated leadership and long-term commitment to this market," said Stefanos Sidiropoulos, CEO of Aeluros. "This commitment, along with the quality and performance of our 10GbE PHY products, has allowed us to gain significant design wins with optical modules and line card customers. Our products are now fully qualified up the value chain (modules, line cards and networking systems vendors) and, are now shipping to end users."
Aeluros will present its patent-pending implementation of VCSEL driver functionality in low voltage CMOS processes in a paper entitled "An Integrated VCSEL Driver for 10Gb Ethernet in 0.13.m CMOS" at the upcoming International Solid-State Circuits Conference (ISSCC) in San Francisco on the 7th Feb during the optical communications session (paper # 13.8). Aeluros will also demonstrate the device at the upcoming OFC/NFOEC conference (Booth # 3283) in Anaheim, CA from 7th - 9th March, 2006.
About Puma AEL100x PHY/SerDes
The Puma AEL100x family includes LAN, FC and WAN PHY devices, is fully IEEE 802.3ae and XENPAK register-set compliant, supports the use of external DOM devices or microcontrollers, and includes integrated PRBS and packet-level test pattern generators and checkers for effective device and module built-in self test (BIST) functions. It also includes the industry-leading low power LAN PHY with only 800 mW power consumption. All the devices maintain the low power features and optimized cost structure made possible by 0.13um CMOS process technology, plastic BGA packaging and expert design techniques, while also achieving SONET/SDH-quality jitter performance in the WAN PHY versions. All members of this family are completely pin compatible, making drop-in replacements straightforward.
About Aeluros
Aeluros, Inc. is a fabless semiconductor company innovating serial, high-performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. For more information about Aeluros, please visit the company's web site at www.aeluros.com.
CONTACT: Siddharth Sheth of Aeluros, Inc., +1-650-917-7062, or sheth@aeluros.com
