IP Core supports RapidIO® 2.1 specification.

Press Release Summary:

Supporting up to 4 lanes at 5.0 GBaud per lane, Serial RapidIO IP Core addresses bandwidth needs of wireless and military markets. Core has been qualified against RapidIO Trade Association's bus functional model, is optimized for 40 nm Stratix® IV FPGAs with embedded transceivers, and is supported within Quartus® II software v9.1.

Original Press Release:

Altera Delivers Industry's First Serial RapidIO 2.1 IP Solution

San Jose, Calif., November 16, 2009-Altera Corporation (NASDAQ: ALTR) today announced the immediate availability of the industry's first intellectual property (IP) core supporting the RapidIO® 2.1 specification. Altera's Serial RapidIO IP core supports up to four lanes at 5.0 GBaud per lane, addressing the increased bandwidth and reliability needs of the wireless and military markets. The IP core is optimized for Stratix® IV FPGAs with embedded transceivers and is supported within Quartus® II software v9.1.

The RapidIO 2.1 specification enables increased performance up to 20 GBaud in applications ranging from next-generation wireless basestations, high-performance military systems and DSP farms. Support for the RapidIO 2.1 specification builds upon Altera's complete Serial RapidIO solution, which includes an end-point IP core that is backward compatible to the RapidIO 1.3 specification, reference designs, application notes, testbenches, and interoperability reports with leading digital signal processor and switch vendors. The Serial RapidIO IP core has been qualified against the RapidIO Trade Association's bus functional model and is supported within Altera's 40-nm Stratix IV GX and Stratix IV GT FPGAs and HardCopy® IV GX ASICs.

"Serial RapidIO is a popular interface for many of our wireless and military customers who put the utmost importance on system bandwidth and reliability," said Luanne Schirrmeister, senior director of component product marketing at Altera. "Combining the industry's first Serial RapidIO IP core supporting the 2.1 specification with Altera's industry-leading FPGA and transceiver technology solidly positions us to address our customer's most important system requirements, including performance, reliability and scalability."

Pricing and Availability

The Serial RapidIO IP solution is part of Altera's MegaCore® IP library and is available now for evaluation upon download and installation of Quartus II software v9.1. To download the combined Quartus II software and MegaCore IP library, visit the download center. Licensing and pricing information for the Serial RapidIO IP core is available by contacting your local Altera sales representative. Additional information on Altera's Serial RapidIO solutions can be found at the RapidIO MegaCore Function page.

About Altera

Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.

Altera, the Altera logo, and all other words that are identified as trademarks are, unless noted otherwise, Registered, U.S. Patent and Trademark Office, and the trademarks of Altera Corporation in the U.S. and other countries. RapidIO is a trademark of RapidIO Trade Association. All other product or service names are the property of their respective holders.

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