IP Core supports 600 Gbps chip-to-chip interface.
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Press Release Summary:
Supporting SerDes data rates up to 28 Gbps and 1-48 lanes, Interlaken IP Controller v6 conforms to Interlaken Retransmit Extension protocol definition and is suited for networking, storage, and high-performance computing products. Unit offers multiple user-data interface options, including 128-bit or 256-bit wide with 1, 2, or 4 segments. In addition, core enables multiple configurations, such as single 600 Gbps interface or four 150 Gbps interfaces, selected at power-up.
Original Press Release:
Open-Silicon Unveils Interlaken IP Core with 600 Gbps Chip-to-Chip Interface Support for Networking, Storage and High-Performance Computing Products
Chip-to-Chip Interface Updates Expand on High-Speed Bandwidth and Flexibility
MILPITAS, Calif., -- Open-Silicon, Inc., a leading semiconductor design and manufacturing company and charter member of the Interlaken Alliance, announced today version six of the company's Interlaken IP core. Networking, storage and high-performance computing products can benefit from the chip-to-chip interface speeds now enabled by the semiconductor industry's first Interlaken IP core to support up to 600 Gbps applications. This release offers tremendous implementation flexibility to customers by supporting SerDes data rates up to 28Gbps and multiple data width options. The IP core also conforms to the recently released "Interlaken Retransmit Extension" protocol definition from the Interlaken Alliance.
Open-Silicon's Interlaken IP provides a scalable, low-risk solution for the high-performance and reliability requirements of networking devices. Proven with silicon success in over 35 implementations, the updated version includes enhancements for increased configurability and flexibility. Customers can benefit from Open-Silicon's flexible business model, which allows for customers to license the IP alone or also take advantage of Open-Silicon's system and physical design services to speed their chip to market.
Open-Silicon Interlaken Controller IP Version 6 Features:
-- Support for retransmit extension protocol introduced by the Interlaken Alliance in September 2011
-- Support for up to 28G SerDes data rates
-- Increased flexibility by allowing a single instance of the core to have multiple configurations (e.g. a single 600Gbps interface or four 150Gbps interfaces) selected at power-up
-- Multiple user-data interface options 128bit or 256bit wide with one, two, or four segments
"Open-Silicon has actively participated in the Interlaken Alliance since its formation in 2007," said Fred Olsson, Interlaken Alliance co-founder. "The Alliance has since created multiple specifications to advance its mission of chip-to-chip interoperability for high-speed packet transfers. I am pleased to see Open-Silicon both take advantage of some of the most recent specification additions as well as drive the bandwidth higher."
"Open-Silicon remains committed to the Interlaken protocol and providing the highest-performance, most scalable Interlaken IP," said Aashish Malhotra, director of IP solutions, Open-Silicon. "We see Interlaken as a standard that is growing from its roots of networking devices to new markets in need of scalable, high-performance, high-bandwidth interface solutions."
About the Open-Silicon ASIC Interlaken IP Core
Developed to incorporate of the benefits of the popular SPI4.2 and XUAI interfaces, Interlaken is a scalable protocol for chip-to-chip packet transfers. High-bandwidth applications, such as those required in networking devices, can utilize the Interlaken protocol to build on the channelization and per-channel flow control features, while reducing the number of chip I/O pins by using high-speed SerDes technology. Interlaken as a protocol has transitioned from the original chip-to-chip interconnect between the network processor and traffic manager to other applications like the extensions to support Interlaken Look Aside as the interconnect for external memory interfaces. Open-Silicon's Interlaken IP can now scale from 10Gbps to over 600Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 28+Gbps) and a variable number of SerDes lanes (1 to 48). This scalability makes Open-Silicon Interlaken ideal for multiple generations of future network switches, routers and storage equipment.
The Open-Silicon Interlaken Protocol Controller IP supports the following Interlaken Alliance specifications:
-- Interlaken Protocol Definition, v1.2
-- Interlaken Look-Aside Protocol Definition, v1.1
-- Interlaken Interop Recommendations, v1.6
-- Interlaken Retransmit Extension Protocol Definition v1.1 Pricing and Availability
Additional details regarding Open-Silicon's Interlaken IP core can be found www.open-silicon.com/ip-and-technology/open-silicon-ip/interlaken-controller-ip.html.
About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, IP, system software, and high-quality semiconductor manufacturing services with one of the world's broadest partner ecosystems for IC development. For more information, visit Open-Silicon's website at www.open-silicon.com or call 408-240-5700.
CONTACT: Hillary Cain, Marketing Manager of Open-Silicon, Inc., +1 408-240-5700, Hillary.cain@open-silicon.com
Web Site: www.open-silicon.com
