Press Release Summary:
Providing 10-60 Gbps bandwidth across interface, Interlaken IP Core features scalable design that makes it suited for future network switches, routers, and storage equipment. Scalability is achieved through combination of SERDES speed of 3.12-6.375 Gbps and 1-24 SERDES lanes. Interlaken protocol combines advantages of SPI4.2 and XAUI interfaces by building on channelization and per channel flow control features of SPI4.2, and reducing number of chip I/O pins by using SERDES technology.
Original Press Release:
SLE, a Tundra Division, Offers High-Speed Interlaken Interconnect Protocol IP Core
EAU CLAIRE, WI, Jan. 23 /- Silicon Logic Engineering Inc. (SLE), a high-end semiconductor design services division of Tundra Semiconductor Corporation today announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs.
SLE's Interlaken IP Core is scalable, with early versions providing from 10Gbps to 60+Gbps bandwidth across the interface. Future versions will provide over 120Gbps of bandwidth. This scalability ideally suits Interlaken for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24).
Designed and tested to be easily synthesizable into many ASIC and FPGA technologies, SLE's Interlaken IP Core was uniquely built to work with off-the-shelf SERDES from most leading technology vendors. Using the vendor specific proven SERDES allows SLE customers to quickly integrate the Interlaken IP Core into the customer's technology of choice.
The open Interlaken specification was co-written by Cortina Systems and Cisco Systems to provide a far more scalable chip-to-chip interface protocol than previous protocols. Interlaken combines the advantages of the popular SPI4.2 and XAUI interfaces by building on the channelization and per channel flow control features of SPI4.2, and reducing the number of chip I/O pins by using high speed SERDES technology, similar to XAUI.
Tundra's Vice President of Design Services, Jeff West, said today "Tundra has again demonstrated leadership on interconnect technologies by adding Interlaken to its portfolio of IP and services and by working with our partners to provide our customers with innovative solutions".
"By working with SLE, customers can take advantage of Interlaken, an open standards high performance system interface for communication equipment," said Zino Chair, Vice President of Marketing, Cortina Systems. "Interlaken enables silicon suppliers to scale their components to 40Gbps and beyond, simplify designs and reduce development cost."
"Users of SLE's Interlaken IP will find that it is easier to evaluate, integrate, and prototype than previous interconnect IP," said Matt Weber, Senior Hardware Engineer and Lead Designer, SLE. "SLE development is well underway and we are currently working with early customers and major ASIC and FPGA vendors to provide Interlaken in multiple technologies, just as we did with our SPI4.2 IP."
The SLE licensable Interlaken IP is available through SLE's sales network. For sales related questions, contact sales at firstname.lastname@example.org or call SLE at 1-908-580-1870.
Tundra Semiconductor Corporation (TSX:TUN) is the global leader in System Interconnect providing world-class support and leading edge semiconductor solutions to the world's foremost communications, networking, storage system, and information technology vendors. Consistently delivering on system level performance promises that reduce time to market, Tundra System Interconnect ensures market advantage in wireless infrastructure, storage networking, network access, military, industrial automation, and information technology applications. Silicon Logic Engineering, Inc. (SLE), a wholly owned subsidiary of Tundra, offers industry-leading semiconductor design services, intellectual property and product development consulting. For more information, visit http://www.tundra.com/.
About Silicon Logic Engineering
Silicon Logic Engineering, Inc. (SLE) specializes in right-first-time design services that address all aspects of ASIC, FPGA and semiconductor system design services. SLE's proven and repeatable Think Physical(TM) design process, tools and semiconductor intellectual property reduce time-to-market and are provided by one of the most experienced VLSI design services teams in the industry. SLE is a division of Tundra Semiconductor Corporation (TSX:TUN). For more information about SLE, please visit http://siliconlogic.com/.
About Cortina Systems
Cortina Systems, Inc. is a leading supplier of intelligent communication solutions thru continuous innovations in advanced port processing and intelligent port connectivity to the Core, Metro, Access and Enterprise Market Segments. With our state of the art high speed analog digital integration, we deliver a wide suite of products that address our customers' performance, density and flexibility needs enabling faster time to- market, longer time-in-market, and increased revenue opportunities. Working closely with our customers to understand their system requirements and anticipate their needs, we are creating the foundation ingredients for new generations of services. For more information about Cortina Systems, please visit http://www.cortina-systems.com/
SLE, the SLE logo and Think Physical are trademarks of Silicon Logic Engineering, Inc. TUNDRA and the Tundra logo are registered marks of Tundra Semiconductor Corporation in Canada, the European Union and the People's Republic of China (Registration is pending in the United States). Design.Connect.Go. is a trademark of Tundra Semiconductor Corporation.
(C) Copyright 2007 Silicon Logic Engineering, Inc. All rights reserved.
Information subject to change without notice.
ASIC: Application Specific Integrated Circuit
High-End ASICs: 90nm or smaller technology, 30 million or more logic gates, with or without challenging power requirements.
FPGA: Field Programmable Gate Array
I/O Pins: Input and Output Pins
IP: Intellectual Property. This news release refers to licensable ASIC or FPGA blocks of intellectual property.
Interlaken: An ultra-scalable chip-to-chip interface protocol written as an open specification by Cortina Systems and Cisco Systems, developed as licensable ASIC and FPGA IP by SLE.
SERDES: A SERDES (serializer/deserializer) transceiver converts parallel data to and from serial data, thereby reducing the number of signals needed in a chip to chip interface.
SPI4.2: The System Packet Interface Level 4 Phase 2 is a high-speed interconnection for 10Gbps aggregate bandwidth applications. The SPI4.2 standard was written by the Optical Internetworking Forum www.oiforum.com/. The SPI4.2 is also abbreviated as SPI-4.2, SPI-4 Phase 2 and SPI Level 4 Phase 2.
VLSI: Very Large Scale Integration
XAUI: A chip-to-chip interconnect using four lanes of 3.125Gbps serial data. XAUI is defined by IEEE802.3ae and used in 10 Gigabit Ethernet (10GbE) systems.