Integrated EDC/10G PHY/SerDes suits 10GBASE-LRM applications.
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Press Release Summary:
Supplied in 15 x 15 mm BGA or 10 x 10 mm packages, 10GbE PHY/SerDes devices feature integrated electronic dispersion compensation (EDC) for 10GBASE-LRM applications. Integrated products offers full PCS, PMA, and XGXS sub-layer functionality for XAUI-based optical modules and SFP+ systems applications. EDC algorithm addresses stress test pulses defined in IEEE 802.3aq specifications for 10GBASE-LRM as well as stringent corner cases that could simulate real world deployment situations.
Original Press Release:
Aeluros Adds New Features to Industry's First Integrated EDC/10G PHY/SerDes for 10GBASE-LRM Applications
Integrated EDC/10G PHY/SerDes for XAUI Modules and SFP+ Applications
MOUNTAIN VIEW, Calif., Dec. 18 -- Aeluros, the leading supplier of low-power CMOS based 10G PHY/SerDes solutions, today announced the availability of its second generation 10GbE PHY/SerDes devices with integrated electronic dispersion compensation (EDC) for 10GBASE-LRM applications. These devices, targeted for both XAUI-based optical modules and the emerging SFP+ systems applications, are built upon the earlier generation of the Puma AEL1003 -- a highly integrated device with full PCS, PMA, and XGXS sub-layer functionality, and all the unique cost-saving features of the previous generation of Puma 10G PHY/SerDes devices, including the industry's lowest power dissipation.
This latest generation of integrated EDC/PHY/SerDes devices from Aeluros incorporates performance enhancements to the original EDC engine that was demonstrated at OFC/NFOEC in March 2006, and participated in the recent industry-wide 10GBASE-LRM interoperability testing. Enhancements include improving the robustness of the EDC algorithm to address not only the standard stress test pulses defined in the IEEE 802.3aq specifications for 10GBASE-LRM, but also more stringent corner cases that could simulate real world deployment situations and identify the real breadth of the EDC engine's performance characteristics.
Aeluros' EDC technology has been extensively tested against various ROSAs (Receive Optical Sub-Assemblies) with different "linear" transimpedance amplifiers from different vendors to ensure interoperability with a variety of configurations that would be encountered in X2 optical modules and SFP+ line-card applications. In addition to the standard IEEE stress tests available through optical testers, Aeluros has tested its EDC technology, with internally developed stress tests, and with high-DMD fiber combined with pre-production SFP+ modules. Aeluros intends to make these tests available to its systems-customers.
"We have focused on developing a very robust EDC engine for our integrated PHY/SerDes devices," said Stefanos Sidiropoulos, Co-founder and CEO for Aeluros. "With a robust EDC function suitable for XENPAK/X2 modules and SFP+-based line-cards, Aeluros is well positioned to address the requirements of both existing and emerging systems architectures."
Samples of the device will be available to Aeluros' modules customers in 15x15mm BGA packages, and to its line-card customers, in 10x10mm packages -- to allow for high-density architectures driven by the emerging SFP+ based system architectures.
About Aeluros
Aeluros, Inc. is a fabless semiconductor company innovating serial, high-performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. Aeluros' list of firsts includes the industry's 1st 10G PHY/SerDes (XAUI) with <1W power consumption.
For more information about Aeluros, please visit the company's web site at www.aeluros.com .
