Integrated 100G EFEC IP Cores optimized for FPGAs.
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Press Release Summary:
With respective overhead ratios of 7% and 20%, EFEC7 and EFEC20 multidimensional enhanced forward error correction (EFEC) IP cores are optimized for Stratix® IV and Stratix V series FPGAs. Functionality targets service providers upgrading 10G metro networks and long-haul OTNs to 100G speeds and planning for future 400G support. Both products leverage Streaming Turbo Product Code BCH code (SPC-BCH) for maximum gain at standard G.709 and provide error free delivery over extended distances.
Original Press Release:
Altera Delivers Industry's First Integrated 100G EFEC Solutions for FPGAs
Enhanced Forward Error Correction Technology Accelerates Migration to 100G
SAN JOSE, Calif. -- Altera Corporation (Nasdaq: ALTR) today announced availability of the industry's first integrated, enhanced forward error correction (EFEC) IP cores optimized for high performance Stratix® IV and Stratix V series FPGAs. The EFEC7 and EFEC20 are multi-dimensional IP cores developed by Altera's Newfoundland Technology Centre (formerly Avalon Microelectronics) and specifically designed for 100G applications such as metro and long-haul optical transport networks (OTN).
Service providers today are upgrading their 10G metro and long-haul OTN networks to 100G speeds to support growing bandwidth requirements for video data, as well as planning for 400G in the future. In addition, these network backbones must operate over 25-50 percent longer fiber spans, while providing lower power, cost, and latency. Altera's EFEC IP cores provide the required performance and error free delivery over longer distances.
"With the combined forecast of the 10G, 40G, and 100G transceiver and transponder market expected to grow to over $2 billion worldwide in 2014(1), we are well positioned to provide high-performance flexible silicon platforms with customizable IP," said Don Faria, senior vice president, Altera Communication and Broadcast Business Division. "Being the first to deliver an integrated, single source 100G solution allows us to ramp-up quickly to meet market demand for the next-generation optical networks."
Altera's EFEC7 and EFEC20 are ultra high gain, hard decision FEC cores that enhance 100G networks and provide the smallest FPGA-based EFEC implementation available in the industry today. The EFEC7 and EFEC20 leverage a Streaming Turbo Product Code BCH code (SPC-BCH) for best in class gain at the standard G.709. At 7 percent and 20 percent overhead ratio respectively, the EFECs provide increased transmission distance and lower transmission power. Altera's SPC-BCH EFECs efficiently solve the implementation complexity issues associated with 100G data rates.
Learn more about Altera's OTN solutions at www.altera.com/end-markets/wireline/applications/otn/wil-optical-transport-network.html or view Altera's EFEC and other product demonstrations in Booth #1551 during OFC/NFOEC 2011 Expo, March 7-9, 2011, in Los Angeles, California, at the Los Angeles Convention Center.
About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.
(1) Infonetics, 2010
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