Fujitsu Introduces Trio of New Macros for ASIC Designs for 90nm and 110nm

New PCI Express, 10G SerDes, Serial ATA Macros Support Server, Wireless, Storage and Desktop Computing Applications

SUNNYVALE, Calif., Aug. 29 // -- Fujitsu Microelectronics America, Inc. (FMA) today expanded its portfolio of IP cores for networking, communications and storage system applications, introducing three new macros for custom ASIC designs.

The new macros include Fujitsu's Serial ATA physical layer storage interface, a 10 Gigabit/second clock data recovery transceiver, and a SerDes macro that is compliant with PCI Express version 1.0a. All three macros can be used in designs built using Fujitsu's 0.11-micron process technology. The PCI Express SerDes and Serial ATA macros have also been designed to be used in 90-nanometer designs. All macros can be applied in customer-owned tooling (COT) and ASIC designs.

"These new macros illustrate Fujitsu's commitment to provide total solutions for our ASIC and COT customers," said Jason So, senior director of FMA's Custom LSI Business Group. "The 10G macro provides customers with the opportunity to enter this challenging design environment using a proven, low-risk, highly efficient core for high-end networking designs. The Serial ATA macro lets users design for the storage and server applications using proven technology, while the PCI Express core delivers the very high bandwidth, excellent quality of service, and reduced power requirements that are essential for new server, desktop and other computing models today."

Serial ATA PHY

The new Serial ATA macro consists of a PHY-control block, PHY core block, and PHY I/O block. The PHY control block interfaces to a link layer equipped with a 16-/20-bit or 32-/40-bit interface. The macro provides cost-efficient STA storage solutions, with advanced data-protection capabilities and support for hard disk drives, network attached storage, servers and other applications. The macro complies with ATA specification revision 2.5 and features two-channel PHY, far- and near-end loopback support, and spread spectrum clock generation, plus AC coupling support. The core block include DCR, PLL generation, 8B/10B encoding and decoding, at-speed built-in self-test, OOB processor and speed negotiation, and integrated 100-ohm matched differential termination.

10Gbps CDR Transceiver

The new 10G macro includes a differential PCML transmitter, reference clock input for PLL, with an LVDS interface, OC-192 jitter tolerance mask, and synchronous data-transfer capability using CDR. Individual channels can be powered down to optimize power usage. The macro includes an on-chip 50-ohm termination for both transmitter and receiver, along with integrated pseudo-random binary sequence generator (PRBS) for test, and software- programmable output current.

PCI Express SerDes Macro

The PCI Express macro, which supports data rates from 2.5Gbps to 3.25Gbps, is ideal for desktop, wireless, server, storage and other applications that require higher bandwidth and lower power consumption than predecessor designs using the PCI standard. This macro incorporates four-channel parallel transmitter and receiver arrays with asynchronous data transfer using dedicated CDR in each receiver channel, and integrates a 50-ohm termination resistor in the receiver and transmitter. Two power-down operations -- dedicated channel and array -- also are supported. The macro operates on 1.2V and 3.3V power supplies; the reference clock frequency is 156MHz to 160MHz.

About Fujitsu Microelectronics America

Fujitsu Microelectronics America, Inc. (FMA) leads the industry in innovation. FMA provides high-quality, reliable semiconductor products and services for the networking, communications, automotive, security and other markets throughout North and South America. For more information about ASICs please see or address e-mail to

Source: Fujitsu Microelectronics America, Inc.

Emi Igarashi
Fujitsu Microelectronics America, Inc.,

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