Flash Memory reduces memory-cell size with 90 nm technology.
Press Release Summary:
NOR Flash Memory Cell occupies silicon area of only 0.08 µm². Increased performance of on-chip peripheral CMOS circuitry enables data to be read from and written to memory array. Reduction in memory cell size corresponds to 40% reduction in die size for 128 Mbit devices, and more for larger memories. Applications include mobile phones, set-top boxes, personal computers, and automotive engine management.
Original Press Release:
STMicroelectronics Announces First 90nm NOR Flash Technology
One of the leading NOR Flash suppliers reports world's smallest NOR flash cell size
Geneva, July 15, 2003 - STMicroelectronics (NYSE: STM), one of the world's leading semiconductor manufacturers, has announced the world's smallest NOR Flash memory cell designed for low voltage and high performance applications. Built in 90nm technology, ST's latest NOR Flash memory cells occupy a silicon area of only 0.08µm2, a 50% size reduction from the current 130nm generation. ST, the world's fourth largest supplier of NOR Flash memories, is also the first of the world's leading NOR Flash suppliers to report successful fabrication of NOR Flash memories in 90nm technology. The new technology has been proven on a multi-megabit demonstrator chip that showed full functionality of entire memory array sectors. In addition, 128Mbit prototype Flash devices were also included on the same development wafers and are now currently under evaluation.
The move to 90nm technology, which is expected to enter volume production in 2004, will maintain ST's aggressive progress in the important market for NOR Flash memories, the largest part of the Flash memory market, which are used in mobile phones, set-top boxes, personal computers, automotive engine management and many other applications.
The new 90nm NOR Flash technology was developed at ST's Center of Excellence for Non Volatile Memories in Agrate, Italy. "This technology provides two major benefits compared with today's 130nm processes: greatly reduced memory cell size and increased performance of the on-chip peripheral CMOS circuitry that enables data to be read from and written to the memory array," said Paolo Cappelletti, Non Volatile Memory Technology Director of Central R&D. "The 50% reduction in memory cell size afforded by the new technology corresponds to a 40% reduction in die size for 128Mbit devices and even more for larger memories, which significantly reduces the cost per bit."
"This latest breakthrough, which is the result of our constant investment in Flash technology, brings us even closer to our ultimate goal of being the technology leader in Flash memory," said Joel Monnier, Corporate Vice-President and Central R&D Director at ST. "In addition, by improving both memory density and CMOS logic performance, the new 90nm technology will further reinforce ST's pre-eminent position in System-on-Chip (SoC) technology, where embedded memories are combined with complex digital and analog circuitry on a single chip."
About STMicroelectronics
STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2002, the Company's net revenues were $6.32 billion and net earnings were $429.4 million. Further information on ST can be found at www.st.com.
