Flash Memory provides data storage for small devices.
Press Release Summary:
Available in both 1.8 and 3 V versions, Models NAND1G and NAND512 offer 1 Gbit and 512 Mbit NAND flash memory. They are organized respectively into total of 32 pages by 4096 and by 8192 nominal blocks that can be read and programmed as a whole. Copy-back program mode enables data stored in one page to be programmed directly into another without external buffering. Each block is specified for 100,000 program and erase cycles, and 10-year data retention.
Original Press Release:
STMicroelectronics Confirms Roadmap for NAND Flash Memory Market with Volume Production of 1-Gbit and 512-Mbit Devices
Availability of high-density NAND Flash memory from ST to provide cost-effective data-storage solutions for USB Flash drives, digital consumer products, MP3 players, cameras and third-generation cell phones
Geneva, March 30, 2004 - STMicroelectronics (NYSE:STM) today announced the volume production of its 1-Gbit and 512-Mbit NAND Flash memory products, which are the first available devices in the company's portfolio of NAND products. The NAND1G and NAND512 are available in both 1.8V and 3V versions.
Demand for NAND Flash memory is driven by emerging Multimedia Systems products, and the major application areas are expected to grow significantly in 2004. NAND Flash memories meet the needs of high volume, physically small products requiring large amounts of data-storage memory, such as removable mass-storage devices for digital cameras, MP3 players, Personal Digital Assistants (PDAs) and third generation (3G) cell phones.
ST's NAND1G and NAND512 provide very high data throughput - the key feature for mass-storage applications - coupled with the high density, fast write time and low power consumption demanded by portable equipment. They are available in two versions for operation on 3.0V (NAND01GW3A, NAND512W3A) and 1.8V (NAND01GR3A, NAND512R3A) power supplies to suit the two major market areas. The 512Mb device is available for 15$ in quantities of 100k units.
Further information on the NAND512 and NAND1G products
The NAND512 and NAND1G memories are organized respectively into a total of 32 pages by 4096 and by 8192 nominal blocks, that can be read and programmed as a whole; the block erase time is just 2ms. The size of the page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The spare bytes are typically used for Error Correction Codes, software flags or Bad-Block identification. A Copy-Back Program mode enables data stored in one page to be programmed directly into another without the need for external buffering, a feature that would typically be used to move the data in the event of failure of a Page Program operation due to a defective block. Each block is specified for 100,000 Program and Erase cycles, and 10-year data retention.
The Address lines and Data Input/Output signals are multiplexed onto an 8-bit bus, reducing the pin count and allowing the use of a modular pin-out which enables system upgrades to higher density devices without changing the footprint. Each device has a Cache Program feature to improve the throughput for large files. This Cache Program loads the data into a cache memory while the previous data is transferred to the page buffer and programmed into the memory array.
Device options include 'Automatic Page 0 Read after Power Up', intended for applications that boot from the NAND memory; and 'Chip Enable Don't Care', which allows the microcontroller to manage NAND operations more efficiently. The 'Chip Enable Don't Care' option also simplifies the use of NAND Flash in combination with other types of memory such as NOR and SRAM - memory combinations are often used where faster devices are needed for code and working memory, but where the much lower cost and higher density NAND memory is preferable for music files or images, for example.
In addition, a unique device identifier can be programmed in-factory, and a User Programmable Serial number supports increased security in the target application. Open source reference software algorithms are available to extend the lifetime of the device, including: Error Correction Code (ECC), to identify and correct errors in the data; Bad Block Management (BBM), to recognize and replace a block that fails in Erase or Program operations by copying its data to a valid block; Garbage Collection, to identify and remove invalid pages in a block and copy valid pages to a free area of another block; and Wear Leveling, to optimize the aging of the device by distributing Erase and Program operations among all the blocks.
The datasheet can be found at the following URL:
http://st.com/stonline/books/pdf/docs/10058.pdf
About STMicroelectronics
STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2003, the Company's net revenues were $7.24 billion and net earnings were $253 million. Further information on ST can be found at www.st.com.
