EDA Software offers SystemC to GDSII flow.
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Press Release Summary:
Integrating Cynthesizer, Blast Create(TM) synthesis, and Blast Fusion® place-and-route technologies, Cynthesizer(TM) v3.3 also includes SystemC behavioral design IP. Graphical interactive analysis environment provides different data views including detailed analysis of control and data flow, register usage, and other hardware details. Software also provides designers with single control to specify level of timing aggressiveness.
Original Press Release:
Forte Announces Cynthesizer 3.3 with First SystemC to GDSII Flow
Adds SystemC Behavioral IP Library and Graphical Analysis Environment
SAN JOSE, Calif., May 25 / -- Forte Design Systems today announced the availability of version 3.3 of its Cynthesizer(TM) SystemC synthesis product. Cynthesizer v3.3 is the first high-level synthesis product to offer a direct path from high-level SystemC to GDSII by integrating Cynthesizer and Magma Design Automation's Blast Create(TM) synthesis technology and Blast Fusion® place-and-route technology. The latest release also adds SystemC behavioral design IP, a graphical analysis environment, and other features for better quality of results (QoR).
"Having a direct link from SystemC algorithms to GDSII provides designers with a significant advantage in time to high quality results," said Sean Dart, Forte's president and CEO. "Our new CynWare IP library and tight integrations with partner products provide customers the fastest path from algorithms to first-time production silicon."
Direct path from SystemC algorithms to GDSII provides timing closure insight
With Forte's integration of Cynthesizer and Magma's Blast Create, designers can take high-level SystemC code and go straight to GDSII, giving them accurate timing and area estimation as early as possible in the design process. Designers can use SystemC for architectural exploration and immediately assess which design will give the best place and route (P&R) utilization. With a few simple configuration settings, designers can automatically use Blast Create to synthesize the Verilog RTL generated by Cynthesizer to a gate-level netlist, and use Magma's Blast Fusion for placement and routing.
At higher levels of abstraction there are less specific implementation details available. Based on feedback from the P&R process, Cynthesizer's timing parameters can be further constrained to meet the implementation requirements without rewriting the original source code. The Cynthesizer SystemC to GDSII flow provides designers with the values of the higher abstraction level while retaining the implementation detail and accuracy.
CynWare: Behavioral level SystemC IP building blocks
With Cynthesizer v3.3, Forte is releasing its CynWare SystemC IP library, giving designers synthesizable building blocks to jumpstart their designs. Since these pre-designed elements are implementation independent, they are re-targetable to different processes or QoR targets without performance or area penalties. The result is truly reusable design IP that accelerates the design and verification process.
The CynWare IP library currently contains synthesizable:
o Floating point datatypes available in IEEE754 single and double
precision as well as other combinations of exponent and mantissa width
defined by the user
o Fixed point datatypes
o Basic connectivity interfaces such as streaming data, FIFO-based, and
memory interfaces
o Master and slave bus interfaces for connection using the AMBA®
AHB(TM)
Transaction-level models (TLM) for fast simulation speeds are included for all interface IP.
Additional Features and QoR optimizations
Forte Cynthesizer v3.3 added the following new features and improvements:
o The Cynthesizer Workbench -- a new graphical interactive analysis
environment that provides a number of different data views including
detailed analysis of the control and data flow, register usage, and
other hardware details all linked to annotated source code views.
Cross-linked views make it easy to analyze details of the design to
understand implementations tradeoffs and make changes for better QoR.
o Advanced Control of Output Port Timing -- allows various output port
timing and register scenarios to be defined, providing fine control
over the exact circuit built to drive the output port and its timing.
o Timing Aggressiveness Control -- allows designers to specify the level
of timing aggressiveness used when processing the design with a single
simple control.
o Design scheduling improvements -- improvements to the underlying
scheduling algorithms that allow Cynthesizer to better implement
designs that include conditional access to multiple memories to reduce
overall design latency.
Pricing and Availability
Cynthesizer v3.3 is immediately available to existing customers without cost. The CynWare IP library has several components some of which are included as part of the Cynthesizer product. Others are priced on a per project basis.
About Forte Cynthesizer
Forte's Cynthesizer significantly reduces the time needed to create complex chips and systems by automatically generating high-quality hardware designs from high-level algorithms. Cynthesizer is silicon-proven with uncompromising quality of results that often exceed hand-coded RTL. Cynthesizer has been used on over 130 designs and is in production use in more than 25 of the top systems and semiconductor companies worldwide.
About Forte Design Systems
Forte Design Systems is a leading provider of software products that enable design at a higher level of abstraction. Forte's innovative high-level synthesis technology allows design teams creating complex electronic systems from algorithmic designs using ASICs, FPGAs, and SoCs to significantly reduce their overall design and verification time. Forte is headquartered at 100 Century Center Court, San Jose, CA 95112. For more information, visit http://www.forteds.com/.
Forte Design Systems is a member of the ARM Connected Community(TM).
Source: Forte Design Systems
CONTACT: Brett Cline of Forte Design Systems, +1-978-264-1855, brett@ForteDS.com;
