Digital Front End Solution enables algorithm design.

Press Release Summary:

TD-SCDMA Digital Front End (DFE) reference design solution enables users to construct 3GPP-compliant DFE designs for base station configurations. System includes full-speed working demo, reference designs, and IP library with optimized System Generator IP Blocks for digital up and digital down conversion functions. Other features include Virtex(TM) -4 platform FPGAs, EVM of 1.6% RMS, ACLR >80 dB, occupied bandwidth of >99.9%, ACS >75 dB, low latency Signal Path Delay of 14.9 µs.

Original Press Release:

Xilinx Announces Immediate Availability of TD-SCDMA Digital Front-End Reference Design

SAN JOSE, Calif., June 20 -- Xilinx, Inc. (NASDAQ:XLNX), the leading FPGA supplier to the wireless infrastructure market, in partnership with the leading radio algorithm developer, Multiple Access Communications (MAC) Ltd, today announced the immediate availability of a TD-SCDMA Digital Front End (DFE) reference design solution based on the Xilinx System Generator for DSP tool. The new reference design solution significantly reduces the development time required for the complex digital algorithms found in TD-SCDMA DFE radio applications. Consisting of example reference designs, full-speed working demo and complete IP library that include optimised System Generator IP Blocks for digital up conversion (DUC) and digital down conversion (DDC) functions, the TD-SCDMA DFE reference design solution enables users to construct 3GPP-compliant DFE designs for a wide variety of base station configurations.

The TD-SCDMA DFE reference design solution enables developers to reduce design risk and provides a quick time-to-market route from concept-to-production for digital radio applications. The IP library encapsulates the signal processing functions that determine compliance with the 3GPP requirements in such a way that complexity of these functions is hidden from the library user. With this approach, developers can save many man-months of algorithm development and many man-years of hardware development time given the multiple antenna and carrier configurations, ranging from single carrier single antenna to 6 carriers 8 antennas per sector.

Dr. Hao-Fei Chen, general secretary of China's TD-SCDMA Forum, said, "As a senior member and the only PLD vendor in the Forum, Xilinx has briefed us on their corporate commitment and technical activities to support, develop and expand the application of TD-SCDMA technology in China. After reviewing the Xilinx TD-SCDMA DFE reference design solution, we are convinced that it can help Chinese companies to shorten their time to market in delivering TD-SCDMA standard compliant wireless base stations of various configurations, from single to multi-carrier designs."

"Xilinx and MAC Ltd have produced a reference design solution that offers a significant time-to-market advantage for OEMs developing TD-SCDMA radio subsystems," said Dr Wilson Oon, senior staff system architect, Wireless Infrastructure, Xilinx Asia-Pacific. "As operators strive to reduce capital and operating costs, wireless OEMs are looking to exploit the lower power and additional flexibility that FPGAs bring to digital radio applications. They are also looking for an architecture that can scale as TD-SCDMA evolves to meet the increasing demand for higher performance and system throughput."

About the Xilinx TD-SCDMA DFE Reference Design Solution

The TD-SCDMA DFE reference design solution is enabled by Xilinx® high-performance VirtexTM -4 platform FPGAs, which offer superior performance and cost-effective DSP processing capability, enabling a lower cost-per-channel than competing solutions. In addition, Virtex platform FPGAs allow in-field upgrades which make the base station more adaptable to evolving technologies and standards.

"The market is looking for flexible, cost-effective solutions which can be developed from concept-to-production as quickly and easily as possible," said David Kenyon, managing director of MAC Ltd. "The combination of the Xilinx Virtex platform FPGA and Mac Ltd's proven expertise in developing wireless signal processing solutions has allowed us to develop a TD-SCDMA DFE reference design that uses FPGA resources very efficiently and fits into very cost-effective devices."

The TD-SCDMA DFE reference design supports up to six carriers per antenna and offers a flexible intermediate frequency input or output. DUC performance highlights are an EVM of 1.6% RMS and Adjacent Channel Leakage Ratio (ACLR) >80 dB, for an occupied bandwidth of >99.9%. The DDC block provides Adjacent Channel Selectivity (ACS) >75 dB, blocking >80 dB and a low latency Signal Path Delay of just 14.9 µs.

Pricing and Availability

The free Xilinx TD-SCDMA DFE reference design is now available for qualified customers at The Xilinx ML402 development board and XtremeDSP(TM) Development Kit for Virtex-4 FPGAs (DO-DI-DSP-DK4) can be purchased separately. Full details on additional options are available at Xilinx also provides a wide range of IP for baseband solutions targeted at W-CDMA, HSDPA and WiMAX industry standards. For more information on the complete line of Xilinx solutions for wireless equipment, visit

About MAC Ltd

MAC Ltd is an established developer of radio solutions and high-performance digital signal processing algorithms across multiple wireless standards. MAC Ltd provides technical consultancy and design services. For further details, see

About Xilinx

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit

FCMN Contact: [email protected] CONTACT: editorial, Dickson Seow of Xilinx Asia Pacific, +65-6580-4948, [email protected]; or Tamara Snowden of Xilinx Public Relations, 1-408-879-6146, [email protected] Web site:

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