"Energizing" Multicore: TI's KeyStone II Architecture Delivers Breakthrough Performance, Greater Integration and Superior Power Savings for Infrastructure and High Performance Applications

28-nm multicore architecture with integrated ARM® A15 cores offers enhanced capacity and performance at less than half the power of traditional RISC cores

BARCELONA, Spain, Feb. 27, 2012 -- MOBILE WORLD CONGRESS -- Texas Instruments Incorporated (TI) (NASDAQ: TXN) today unveiled significant updates to its award-winning KeyStone multicore architecture, paving the way for a new era of high performance 28-nm devices that meld signal processing, networking, security and control functionality. Ideal for applications that demand superior performance and low power, TI's scalable KeyStone II architecture includes support for both TMS320C66x digital signal processors (DSP) generation cores and multiple cache coherent quad ARM Cortex(TM)-A15 clusters, for a mixture of up to 32 DSP and RISC cores. Devices based on the KeyStone architecture are optimized for high performance markets including communications infrastructure, mission critical, test and automation, medical imaging and high performance and cloud computing. For more information, please visit www.ti.com/multicore.

"Network operators and OEMS are being increasingly challenged to deliver significantly higher bandwidth network infrastructure on more energy-efficient and compact platforms," said Lance Howarth, executive vice president of marketing, ARM. "The introduction of TI's industry leading, highly scalable, multicore platform, utilizing the Cortex-A15 processor, is going to considerably lessen those challenges enabling OEMs to deliver a new generation of energy efficient network infrastructure solutions."

Compared with TI's 40-nm KeyStone multicore DSPs and System-on-Chips (SoCs), KeyStone II devices offer developers more than twice the capacity and performance and a substantial boost in power performance ratio. TI's KeyStone II architecture includes capacity expansion for SoC structural elements such as TeraNet, Multicore Navigator and Multicore Shared Memory Controller (MSMC). This expansion allows developers to fully utilize the capability of all processing elements, including ARM RISC cores, DSP cores and enhanced AccelerationPacs. RISC processing within KeyStone II has been significantly upgraded with the addition of quad ARM Cortex -A15 clusters, providing ultra-high performance at half the power consumption of traditional RISC cores. This breakthrough will enable the creation of high performance "green" network infrastructure equipment.

KeyStone II is initially targeted at upcoming 28-nm devices for wireless infrastructure applications. The architecture features rich hardware AccelerationPacs for multi-standard Layer 1 baseband functionalities and network and security acceleration for Layer 2, 3 and transport functions. AccelerationPacs are designed for autonomous operation, minimizing the need for either DSP or ARM core intervention and reducing latencies. Keystone II's Multicore Navigator has also been enhanced, providing 16K hardware queues, one million descriptors and built-in hardware intelligence for scheduling and load balancing. The architecture includes an enhanced shared memory controller with 2.8Tbps switching capability, providing low latency access to shared internal and external memory, and also features a 2.2Tbps TeraNet switch fabric, delivering industry-leading non-blocked data movement between all on-chip processing elements and resources. Together, these features provide full multicore entitlement for heterogeneous network solutions.

Energizing base station processing with new KeyStone II SoC In addition to unveiling the KeyStone II multicore architecture today, TI announced its first KeyStone II device, the TMS320TCI6636. The TCI6636 SoC includes the first and fastest quad ARM Cortex-A15 RISC processors, offering wireless base station developers more than twice the capacity and ultra-high performance at half the power consumption of traditional RISC cores. It also leverages 28-nm silicon process to integrate a mix of processing elements including eight TI fixed- and floating-point TMS320C66x DSP generation cores, as well as enhanced packet, security and wireless AccelerationPacs. Together these processing elements, with the integration of field-proven layers 1, 2, 3 and transport processing, and operation maintenance and control processing, reduce system cost and power consumption, supporting the development of more cost-efficient, green base stations. To view the announcement, please visit www.ti.com/multicore.

Visit TI @ Mobile World Congress
While at MWC, visit TI at Booth 8A84 (Hall 8) to learn more about the latest communications infrastructure, analog, wireless and DLP news, and to check out a broad range of TI based demos. For more information please visit www.ti.com/mwc2012.

For more information:

-- Watch TI's KeyStone video and Ask The Experts series

-- Engage with engineers and TI experts on the TI E2E(TM) Community and
Multicore Mix

-- Follow TI on Twitter

-- Become a fan of TI on Facebook

About TI's KeyStone multicore architecture Texas Instruments' KeyStone multicore architecture is the platform for true multicore innovation, offering developers a robust portfolio of high performance, low-power multicore devices. Unleashing breakthrough performance, the KeyStone architecture is the foundation upon which TI's new TMS320C66x DSP generation was developed. KeyStone differs from any other multicore architecture as it has the capacity to provide full processing capability to every core in a multicore device. KeyStone-based devices are optimized for high performance markets including wireless base stations, mission critical, test and automation, medical imaging and high performance computing. Learn more at www.ti.com/multicore.

About Texas Instruments

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