Aeluros Wins Challenging Line-Card Design With Its 10G LAN/WAN PHY
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MOUNTAIN VIEW, Calif., Feb. 21 -- Aeluros, the leading supplier of low-power CMOS based 10G PHY solutions, today announced that High Performance Ethernet Switch Router vendor Force10 Networks has chosen Aeluros' 10G PHY devices for its next generation high-density 16-port 10GbE LAN/WAN PHY line card on its E1200 systems. These 2nd generation 10G PHY devices are pin compatible with Aeluros' industry leading 800mW Puma AEL1001/AEL1002 device family, providing a complete portfolio of 10 Gbps-to-XAUI devices for optical module and line card applications.
The Puma AEL1004 and AEL1005 products -- optimized separately for XAUI modules and line cards -- are the LAN/WAN PHY version of the Puma product family of 10GbE PHY/SerDes devices. They incorporate on-board clock synthesizers that eliminate the need for board designers to provide two clock sources for Ethernet and SONET/SDH rates -- by allowing the Ethernet clock to be synthesized from the SONET clock source. With this patent-pending design approach, a single clock input of 155.52MHz (optional support for a single 50 MHz CMOS clock source) is sufficient to drive both the SONET/SDH and Ethernet/XAUI clocking requirements in the device. Additionally, on-board clean-up circuitry also allows the device to provide stratum-3 level line- timing capability for SONET/SDH timing requirements.
"Aeluros' approach to developing 10G LAN/WAN PHY devices with an attractive combination of low power, small size and cost saving features like the on-board clocking synthesizers was key to our decision to pick Aeluros' PHY devices for our dense 16 port line card," said Mike Laudon, Director of Hardware Engineering at Force10 Networks. "Additionally, Aeluros' design-in tools, including reference designs, detailed design guidelines and their committed on-site technical support, made the task of designing the 10G line card easier."
"We are very pleased that Force10 Networks has chosen the Aeluros 10G LAN/WAN PHY device for its more challenging 16 port line card," said Stefanos Sidiropoulos, CEO of Aeluros. "The increasing functionality of our 2nd generation CMOS devices -- in pin compatible form to the earlier AEL1001/1002 devices -- demonstrates our commitment to staying ahead of our competition and providing the customer base with a complete portfolio of 10G PHY devices with very attractive features."
About Puma AEL100x PHY/SerDes
The Puma AEL100x family includes LAN, FC and WAN PHY devices, is fully IEEE 802.3ae and XENPAK register-set compliant, supports the use of external DOM devices or microcontrollers, and includes integrated PRBS and packet-level test pattern generators and checkers for effective device and module built-in self test (BIST) functions. It also includes the industry-leading low power LAN PHY with only 800 mW power consumption. All the devices maintain the low power features and optimized cost structure made possible by 0.13um CMOS process technology, plastic BGA packaging and expert design techniques, while also achieving SONET/SDH-quality jitter performance in the WAN PHY versions. All members of this family are completely pin compatible, making drop-in replacements straightforward.
About Aeluros
Aeluros, Inc. is a fabless semiconductor company innovating serial, high-performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. For more information about Aeluros, please visit the company's web site at www.aeluros.com.
Source: Aeluros, Inc.
CONTACT: Siddharth Sheth of Aeluros, Inc., +1-650-917-7062, or sheth@aeluros.com
Web site: www.aeluros.com/
