IPFlex Inc.
Burlingame, CA 94010
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Image Processor IC is dynamically reconfigurable.
Supplied in 1,156-pin TE-BGA package, DAPDNA-IMS dynamically reconfigurable processor (DRP) is designed for image processing in office automation applications. Flexible programmable logic chip is based on Digital Application Processor/Distributed Network Architecture (DAPDNA) and can change its hardware functionality in 5 ns utilizing 32-bit RISC core controller and heterogeneous matrix of 955...
Read More »Image Processor IC is dynamically reconfigurable.
Supplied in 1,156-pin TE-BGA package, DAPDNA-IMS dynamically reconfigurable processor (DRP) is designed for image processing in office automation applications. Flexible programmable logic chip is based on Digital Application Processor/Distributed Network Architecture (DAPDNA) and can change its hardware functionality in 5 ns utilizing 32-bit RISC core controller and heterogeneous matrix of 955...
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