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SoC Design Software supports OpenCL kernels.

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April 29, 2014 - Accelerating runtimes and optimizing QoR, Vivado® Design Suite 2014.1 automates UltraFast™ design methodology best practices for 28 nm 7 series and 20 nm UltraScale™ All Programmable devices. Software automates correct-by-construction constraints with interactive timing constraint wizard. Vivado High-Level Synthesis provides hardware acceleration of OpenCL kernels and enables C, C++, and System C specifications to be directly targeted into devices without need to manually create RTL.

Vivado Design Suite 2014.1 Increases Productivity with Automation of UltraFast Design Methodology and OpenCL Hardware Acceleration


Xilinx, Inc.
2100 Logic Dr.
San Jose, CA, 95124 3400
USA



Press release date: April 16, 2014

New release delivers faster runtimes, improved QoR, OpenCL kernel support and automates UltraFast design methodology best practices for 7 series and UltraScale All Programmable devices

SAN JOSE, Calif. -- Xilinx, Inc. (NASDAQ: XLNX) today released the Vivado® Design Suite 2014.1, the industry's only SoC-strength development environment. This release extends the automation of the UltraFast(TM) design methodology and delivers an average of 25 percent faster runtimes and 5 percent improvement in performance across all devices. Also new to 2014.1 is hardware acceleration of OpenCL kernels, within Vivado High-Level Synthesis (HLS).

With over 2,500 customers trained on the UltraFast design methodology and 30,000 views of the UltraFast design methodologyvideo tutorial, Xilinx continues to raise awareness and adoption of the methodology developed to increase designer productivity. By leveraging the UltraFast design methodology recommendations design teams are achieving design closure in weeks versus months spent on similar projects without this methodology.

Now in its second edition, the UltraFast design methodology has been extended to include new best practices for Vivado's support of 28nm 7 series and 20nm UltraScale(TM) devices. The UltraScale architecture applies leading-edge ASIC techniques in a fully programmable architecture to enable multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates, scaling to terabits and teraflops . The updated methodology also includes high-level synthesis, partial reconfiguration, and verification using the Cadence, Mentor Graphics, and Synopsys flows.

Tool Enhancements
Critical to improving productivity with the UltraFast design methodology best practices is correctly constraining a design to achieve rapid timing closure. The Vivado Design Suite 2014.1 automates correct-by-construction constraints with the release of a new interactive timing constraint wizard. Intelligence built into the wizard queries the Vivado design database to extract the clocking structure as well as existing constraints, often coming from IP reuse, then guides the user to correctly constrain the rest of the design.

Also introduced with this release is the new Xilinx Tcl Store where the design community can freely publish and share qualified scripts that perform useful functions and improve productivity. The Tcl store is fully accessible within the Vivado Integrated Design Environment and provides an open source repository where designers can make use of scripts that perform functions which extend Vivado Design Suite core capabilities, and tool experts can share code that improves the efficiency of the larger user community.  Available today are Tcl applications that provide custom reports, analysis, optimizations, tool flow control, and design changes.

Vivado High-Level Synthesis
Used today on advanced algorithms found in wireless, medical, defense, and consumer applications for accelerating IP creation, Vivado HLS enables C, C++ and System C specifications to be directly targeted into Xilinx® All Programmable devices without the need to manually create RTL. The combination of Vivado IP Integrator and Vivado HLS can significantly reduce development costs--by as much as a factor of 15--versus an RTL approach.With the Vivado Design Suite 2014.1 release, Vivado HLS now offers early access support of OpenCL kernels. OpenCL provides a framework and language for writing kernels that executes across heterogeneous platforms and can now be seamlessly converted to IP running on Xilinx All Programmable devices.  Additionally, this release extends Vivado HLS for signal processing applications with a new linear algebra library, enabling rapid IP generation of C/C++ algorithms that require functions such as Cholesky decomposition, singular value decomposition (SVD), QR Factorization, and matrix multiplication. 

Availability
Download the Vivado Design Suite 2014.1 today at www.xilinx.com/download. For all release updates including enhancements to Xilinx SDK (Software Design Kit)  and updates to Xilinx IP, see the release notes. Sign up for or view online training for Vivado Design Suite, and take advantage of the UltraFast design methodology and the Vivado Design Suite-based Targeted Reference Designs to jumpstart your productivity.

About Xilinx
Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit www.xilinx.com.

© Copyright 2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Xilinx
Silvia E. Gianelli
(408) 626-4328
silvia.gianelli@xilinx.com
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