Memory Modeling Software creates behavioral models to speed verification.June 17, 2009 -
Used to generate behavioral models for memory vendors such as Micron®, Samsung®, Hynix®, and Elpida®, DDR2 SDRAM SystemVerilog Memory Model Generator helps accelerate design processes by offering simulation models and verification environments. GUI- and HVL-based tool makes it possible to configure parameters of DDR2 SDRAM memory, such as memory size, data width, clock rate, cycle time, CAS latency, and data rate. It can be operated in Typical or Custom modes.
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Original Press release
eInfochips, Inc.
4655 Old Ironsides Dr., Suite 385
Santa Clara,, CA, 95054
USA
eInfochips Announces DDR2 SDRAM SystemVerilog Memory Model Generator Tool
GUI-Based Tool Reduces Verification Time and Maximizes Memory Coverage
SUNNYVALE, California and AHMEDABAD, India, June 4 -- eInfochips, Inc., a leading design services company today announced the availability of a DDR2 SDRAM SystemVerilog Memory Model Generator. This HVL-based tool is an integrated solution to generate behavioral models for all leading memory vendors, such as Micron(R), Samsung(R), Hynix(R) & Elpida(R), thereby shortening verification time & maximizing memory coverage.
"eInfochips strives to market solutions that add value to the design process," states Sribash Dey, VP, North America Sales at eInfochips. "By offering high-quality simulation models and verification environments, we believe the DDR2 SDRAM memory model generator tool will reduce overall verification time and reduce development cost."
With eInfochips' DDR2 SDRAM model generator, it is possible to configure parameters of DDR2 SDRAM memory such as memory size, data width, clock rate, cycle time, CAS latency and data rate.
Key Features of Memory Generator Tool
The DDR2 SDRAM memory generator is a TCL/TK-based tool that supports leading memory vendors and preserves a large library of part numbers for each supported memory vendor. The tool can be operated in 2 modes - Typical Mode or Custom Mode. In the Typical Mode, a user may choose vendors and part numbers to generate the memory model. In the Custom Mode, a user may create a customized behavioral model from scratch by configuring the parameters of DDR2 SDRAM through the configuration selection algorithm (CSA).
Key Features of Generated Behavioral Models
The behavioral models are compliant to JEDEC standard JESD79 - 2D and ready to be plugged into a verification environment. The models offer built-in coverage and can be configured to turn on/off initialization, enable/disable DDR2 interface checkers and coverage.
Deliverables
Deliverables include verified SystemVerilog DDR2 SDRAM generator encrypted code, a user guide and release notes.
For more information on this IP please visit: http://einfochips.com/services/asic/IP/ddr2-sdram-memorygenerator-systemv
erilog.php
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Support & Availability
DDR2 SDRAM SystemVerilog memory generator tool is now available and comes with support. For pricing details write to us at sales@einfochips.com Currently the tool supports DDR2 but is expandable to support DDR, DDR3, NAND Flash, NOR Flash, QDR, XDR.
About eInfochips
eInfochips is a leading IP driven design services company with the range of services & solutions in ASIC/Chip/SoC, Embedded System and Software. eInfochips' Chip/ASIC group has capabilities spanning from ASIC/Chip design, verification, physical design, FPGA design & prototyping and IP Cores development and integration. eInfochips has contributed to over 130+ designs in automotive, consumer, semiconductor, avionics, networking/communication, video and security/surveillance industries through its wide array of RTL to GDS II services and solutions. For more information, visit http://www.einfochips.com
Micron(R), Samsung(R), Hynix(R) & Elpida(R) are trademarks of Micron Technology, Samsung, Hynix Semiconductor Inc. and Elpida Memory Inc respectively. Other names and brands may be claimed as the property of others.
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