Host Controller supports SDIO Specification 2.0.February 12, 2009 -
Available as single IP core, SDIO-HOST is suited for any memory card or SDIO application. Support for CPRM mechanism is realized through implementation of Cryptomeria cipher algorithm for symmetric data encryption. With set of wrappers for AMBAŽ AHB, APB, Avalon, and Wishbone, core can be reused in different design environment within one multiuse license. Support for MMC 4.2 guarantees compatibility with MMC-Plus memory cards, and enables data transfer rates to 400 Mbit/s.
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Original Press release
Evatronix SA
ul. Przybyly 2
Bielsko Biala, ,
Poland
Evatronix Upgrades its SDIO Host Controller with the Full Support for CPRM, MMC 4.2, and SDIO Specification rev. 2.0
These and other advancements make the IP core a perfect solution for any memory card or SDIO application.
Gliwice & Bielsko-Biala, Poland, November 3rd, 2008 - The Silicon Intellectual Property (IP) provider, Evatronix SA, announced today the upgraded SDIO-HOST - a full SDIO specification 2.0 compliant host controller. Moreover, a variety of spec-independent enhancements add up to the overall value and performance of the product, making it one of the most complete memory controllers available as a single IP core.
Support for Content Protection for Recordable Media (CPRM) mechanism is realized through the implementation of the Cryptomeria cipher (C2) algorithm for symmetric data encryption. Authentication Key Exchange (AKE) and Media Key Blocks (MKBs) processing are also done in hardware.
The new version of the SDIO-HOST is another extension to the Evatronix' list of Open Core Protocol (OCP) enabled IP cores. With a set of wrappers for AMBAŽ AHB, APB, Avalon, Wishbone and others, the core can be easily reused in a totally different design environment within one multiuse license.
Support for MMC 4.2 guarantees the IP core's compatibility with the newest MMC-Plus memory cards, and thus increases the maximum data transfer rates to 400 Mbit/s.
The Advanced DMA module resides inside the core next to the regular DMA engine for even more significant relief of the system CPU from tasks related to SDIO device control. Its descriptor based (scatter-gather) architecture provides non-contiguous data buffer alignment that allows various memory allocation options.
"This extensive upgrade to our SDIO solution shows our constant drive to supply our customers with products that are compatible with the newest standards," said Tomasz Kowalczyk, the SDIO Product Manager at Evatronix. "The second generation of SDIO-HOST is packed with features that will both facilitate the IP core's integration in any System-on-Chip and make it future-proof. With the latest extensions we are able to meet customers needs in almost every SDIO based application."
Availability and customization options
The upgraded version of the SDIO-HOST IP core is available for licensing now. While a standard delivery includes every above described feature, Evatronix is ready to trim or extend the core's functionality to meet customer's requirements. An extensive testbench with an SD memory card HDL simulation model is provided for successful System-on-Chip integration.
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