Bus Interface Libraries connect HLS models to ARM platform.
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Press Release Summary:
Bus Interface Libraries connect hardware subsystems implemented with High Level Synthesis (HLS) product, Catapult® Synthesis, with AMBA® AXI(TM) bus interfaces. Libraries include master and slave interfaces with both transaction level modeling and HLS views, allowing interplay between TLM 2.0 platform and HLS implementation flow without degrading simulation performance. Parameterizable AXI interface supports range of configurations including burst modes, bus width, and auxiliary control signals.
Original Press Release:
Calypto Delivers Bus Interface Libraries to Easily Connect High Level Synthesis Models to ARM Platform
SANTA CLARA, Calif., - Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, today announced bus interface libraries that connect hardware subsystems implemented with Calypto's High Level Synthesis product (HLS), Catapult® Synthesis, with AMBA® AXI(TM) bus interfaces. The libraries include master and slave interfaces with both Transaction Level Modeling (TLM) and HLS views, which allows easy interplay between a TLM 2.0 platform and HLS implementation flow without degrading simulation performance or hardware quality. The highly parameterizable AXI interface supports a wide range of configurations including burst modes, bus width and auxiliary control signals.
"The AXI interfaces are the first in a series of libraries in development at Calypto that will make Catapult C more readily available to mainstream designers," said Shawn McCloud, Vice President of Marketing at Calypto. "They are written entirely in SystemC and tuned through the Catapult C synthesis tool. These interfaces are a great example of the benefits of mixing cycle accurate SystemC for control with abstract SystemC/C++ to implement a hardware subsystem."
The AXI interface library is tuned so the resulting hardware is optimized for the user's specific performance requirements, configuration mode and target technology. Availability in April, please contact Calypto Sales for specific pricing and information.
About Calypto's Products
Catapult High Level Synthesis, Calypto's SLEC® (Sequential Logic Equivalence Checking) and PowerPro® platforms are used by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto's products enable electronic system level design by engineers to dramatically improve design quality and reduce power consumption of their system-on-chip (SOC) devices.
About Calypto
Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. More information can be found at www.calypto.com.
Acronyms
AMBA: Advanced Microcontroller Bus Architecture
AXI: Advanced eXtensible Interface
ESL: Electronic System Level
HLS: High Level Synthesis
RTL: Register Transfer Level
SOC: System on Chip
TLM: Transaction Level Modeling
Catapult, Calypto, PowerPro and SLEC are trademarks of Calypto Design Systems Inc.
All other trademarks are property of their respective owners.
