Parallel Processor supports digital video applications.
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Press Release Summary:
ConnexArray vector architecture combines thousands of RISC-like processing elements with local memory on a single chip. Massively parallel architecture functions with 16-bit integer and Boolean operations to execute data-intensive algorithms necessary to encode, decode, and transcode multiple HDTV channels. Developers can use SDK to write programs in Connex Programming Language (CPL), an extension of C that adds vector datatype for parallel operations on video datastreams.
Original Press Release:
Connex Technology Unveils Architecture for Programmable, Massively Parallel Processors, Optimized for HDTV
Comparable to Fixed-functioned ASICs in Performance and Cost
LOS GATOS, Calif., May 17 /-- Connex Technology, developer of the ConnexArray(TM) Programmable Video Platform (PVP), today announced the patented ConnexArray vector architecture which combines thousands of simple, RISC-like processing elements (PEs) with local memory on a single chip. The massively parallel architecture is perfectly suited to the data-parallel processes inherent in digital video, and it enables processors to execute the data-intensive algorithms necessary to encode, decode, and transcode multiple HDTV channels. The processors are as silicon efficient as most ASIC chips, comparable in cost and performance, and perform far better than competitively priced DSP solutions. Unlike ASICs, ConnexArray chips are fully programmable and can support different and evolving digital-video standards, enable multiple product personalities, and preserve intellectual property.
"ConnexArray is the architecture of the future for HDTV," said Paul Vroomen, President and Chief Executive Officer of Connex Technology. "This market will experience strong growth in the next few years as the prices of flat panel displays fall and as broadcasters follow the government mandate to phase out analog broadcasting. Since ConnexArray functions are quickly and inexpensively modified with software, the chips will be extremely attractive to developers responding the massive turnover in televisions and the inevitable demand for more sophisticated HDTV products."
ConnexArray delivers high performance and high-level programmability by focusing on data parallelism with a massive array of simple and identical PEs -- over 4,000 in the successful 2003 test chip and 1,024 in the upcoming commercial chip. Connex's basic idea is to stay simple and optimize the arrays for the narrow domain of high-definition digital video.
The Connex Array PEs contain no features unnecessary for the parallel operations of video decoding -- i.e. no multiply-accumulate instructions (MACs), no floating point hardware, etc. The PEs function with a simplified set of about 70 instructions -- 16-bit integer and Boolean operations -- and can collaborate in software-controlled configurations to execute different algorithms and handle different workloads. The PE array's size and I/O controller's bandwidth are matched to the workload and target algorithms. Developers can use the complete software development kit (SDK) to write programs in the Connex Programming Language (CPL), an extension of C that adds a new vector datatype for parallel operations on video datastreams. Programs make use of an on-chip memory controller that vectorizes the serial datastream for the parallel processor array.
Unlike most massively parallel processors, ConnexArray does not rely on mesh-like interconnect fabrics to enable multidirectional communication between PEs. Mesh fabrics require complex webs of wiring that can take up more area of the die than the PEs themselves. The size of such fabrics must often be limited due to delays in signal propagation, which lowers processing power. Connex avoids complex wiring and simplifies on-chip interaction by allowing each PE to communicate with only two other PEs in a serial chain. Connex's first commercial chip will have a two-dimensional array of 16 x 64 PEs. Although other sizes and configurations are possible, 1,024 PEs will be more than sufficient to simultaneously decode two channels of H.264 video at HD resolution.
About Connex Technology
Based in Los Gatos, California, Connex Technology has developed a patented vector processing architecture known as ConnexArray(TM). This disruptive massively parallel processor-in-memory architecture enables exciting new capabilities in digital signal processing. Boasting a silicon efficiency that rivals that of ASICs, the ConnexArray family of media processor SoCs addresses the spiraling costs of ASIC development by finally offering the cost efficiency of ASIC and 100% software programmability at the same time. Additional information is available online at www.connextechnology.com
Source: Connex Technology
CONTACT: Sabrina Joseph of Morphoses Inc. Public Relations,
+1-408-726-1577 or connexpr@morphoses.com, for Connex Technology
Web site: www.connextechnology.com/
