4DSP Inc.
Reno, NV 89502
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IP Core for FPGA is designed for programmable devices.
Based on radix-32 architecture, IEEE-754-compliant Floating Point Fast Fourier Transform core transforms complex data ranging from 256 to 1 million points with external memory, if necessary, such as QDR SRAM. Users can change transform length on-the-fly, without reconfiguring programmable device. In chips such as Altera Stratix-II and Xilinx Virtex-4 FPGAs, 4 cores can be implemented in parallel...
Read More »IP Core for FPGA is designed for programmable devices.
Based on radix-32 architecture, IEEE-754-compliant Floating Point Fast Fourier Transform core transforms complex data ranging from 256 to 1 million points with external memory, if necessary, such as QDR SRAM. Users can change transform length on-the-fly, without reconfiguring programmable device. In chips such as Altera Stratix-II and Xilinx Virtex-4 FPGAs, 4 cores can be implemented in parallel...
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