Cores

RISC Processor Core comes with software development tools.

Suited for ASIC and FPGA applications, 32-bit XAP3 features Von Neumann architecture that allows code and data to be freely mixed within flat 4 GB memory space. Development tools, which include Gnu Compiler Collection, C/C++ compiler, and uCLinux and Micrium -µC/OS-II RTOS, provide support for embedded system applications. Core is available in Verilog RTL for ASIC use, can be fabricated in...

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Spectrometer IP Core suits radio astronomy applications.

Spectrometer IP core for FPGA enables development of wideband spectral analysis systems. Based on HyperSpeed Fast Fourier Transform (FFT) technology, core takes 1 GHz sampled signal at its input and converts it to frequency power spectrum using digital band filter and 16K-point FFT in continuous real-time. This process enables 400 MHz bandwidth of radio spectrum with passband ripple of 0.001 dB...

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VoIP Solutions facilitate voice-enabled product development.

Z.Voice(TM) solutions provide time-efficient way to voice-enable products, and include licensable ZSP-® processor cores, DSP products, industry-compliant vocoders, bundled silicone/software packages, and reference designs. Products enable multi-channel VoIP solutions that support range of 2-32 channels of VoIP. Z.Voice-729 Bundle provides take-to-market G.729, G.729A/B, multi-channel VoIP...

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Pot Core Inductors feature high inductance.

Pot Core Inductors feature high inductance.

POWER POTS(TM) Series RL-7300 has 23 standard values for each of 5 different sizes. Units offer inductances from 10 mH to 1 H and handle currents from 12 mA to 1 A. Pot core design is capable of handling dc currents while maintaining stable inductance due to high saturation currents and self-shielding. Typical applications include dc chokes, differential mode chokes, filters, switching circuits,...

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Embedded Processor is available in 3 versions.

Nios-® II family consists of three 32-bit RISC embedded soft-core processors that deliver more than 200 DMIPS: one for maximum system performance, one optimized for minimum logic usage, and one in-between. All cores are 100 percent code compatible and include software development suite with compiler, IDE, JTAG debugger, MicroC/OS-II RTOS, and TCP/IP stack. Developers can also add up to 256...

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Video Core targets digital television applications.

Model CS7050 high-definition H.264/AVC hardware video decoder core supports wide range of image resolutions, both HD and ST at Main Profile up to Level 4.1. Unit includes direct interfaces to SoC memory control system for storage of reference and decoded pictures in system-wide shared memory. Available on both ASIC and FPGA technologies, core decodes Main Profile video streams at resolutions up...

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Processor Cores are based on 8-stage pipeline.

Series MIPS32-® 24K(TM) 32-bit, 550 MHz synthesizable processor cores offer 1.44 Dhrystone MIPS/MHz performance in core area of less than 3.0 mm-². Development support includes tailored, front-to-back-end design methodologies and standard, Open Core Protocol interconnect structure. Hardware branch prediction is present to keep pipeline supplied with instructions. Units are targeted at broadband...

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FFT IP Core is suited for FPGA co-processors.

Fully integrated fast Fourier transfer (FFT) IP core, FFT MegaCore-® Function 2.0, enables system designers to off-load computationally intensive FFT functions to FPGA co-processor. It delivers up to 16 K points of resolution as well as max clock frequency in excess of 300 MHz. IP core, comprised of FFT, data RAM, and twiddle ROM, includes IP toolbench GUI and quad-output Radix 4 FFT engine that...

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Embedded DSP Core runs above 600 MHz.

Based on Model ST100 DSP architecture, Model ST122 Dual MAC core is supported by evaluation chip fabricated in 130 nm technology and complete development platform. It can be mapped into versions ranging from ultra-low power to high-speed operation. Flexible instruction modes allow mixture of 16, 32 and 128-bit instructions. Evaluation device includes 16 kbytes of L1 Program cache, 256 kbytes of...

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Microarchitecture lays foundation for synthesizable cores.

MIPS32(TM) 24K(TM) provides single issue, 8-stage pipeline; hardware-based cache coherency to support multi-processor scaling; configurable memory management unit with TLB or fixed mapping; and 64-bit memory subsystem with up to 6 read transactions. Cores based on microarchitecture offer 400-500 MHz performance in 0.13 -µm process.

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