Cores

Altera, Sarance Technologies and Cortina Systems Join Forces on First Interlaken Protocol IP Core for FPGAs

Targets High-Speed Networking and Storage Equipment, Demonstrates Stratix II GX FPGA Capability in 6.375-Gbps Applications San Jose and Sunnyvale, Calif., and Ottawa, Ontario, August 14, 2006- Altera Corporation (NASDAQ: ALTR), design services provider Sarance Technologies and communications semiconductor specialist Cortina Systems today announced the availability of the industry's first...

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Altera and Elektrobit Offer First OBSAI RP3-01 Development Kits for Wireless Base Station Designs

San Jose, Calif. and Oulunsalo, Finland, August 15, 2006-Altera Corporation (NASDAQ: ALTR) and Elektrobit Group Plc. (HEX:EBG1V) today announced the availability of the industry's first development kits for designing applications in compliance with the Open Base Station Architecture Initiative (OBSAI) Reference Point 3-01 (RP3-01) specification for remote RF heads. The kits include a Stratix® II...

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Processor Core powers 8-bit-compatible, 32-bit MCUs.

For optimal system utilization, 68K/ColdFire-® V1 core powers 8-bit compatible 32-bit devices and facilitates migration between architectures. Products based on V1 core will use same peripheral modules and development tools as products based on S08 architecture, including CodeWarrior-® 6.0 development studio. Along with built-in ColdFire architecture registers, product uses S08 bus structure to...

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USB 2.0 nanoPHY IP is suited for handheld electronics.

DesignWare-® USB 2.0 mixed signal nanoPHY intellectual property (IP), built for Taiwan Semiconductor Manufacturing Company's (TSMC's) Nexsys 90 nm low-power (LP) process, is tunable for optimal yield by enabling adjustments in key PHY performance parameters. Hi-Speed USB logo-certified product has single-port, on-the-go (OTG) configuration that takes up 0.6 mm-² and consumes less than 30 mA of...

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IBM and Chartered Team with Synopsys for Mixed-Signal Connectivity IP at 65 nm

Synopsys USB, PCIe, SATA and XAUI PHYs for High-Volume, Low-Power Applications Available for Foundries' Leading-edge Processes MOUNTAIN VIEW, Calif., July 11 / -- Synopsys, Inc. (NASDAQ:SNPS), a world leader in semiconductor design software, today announced that IBM and Chartered Semiconductor Manufacturing have agreed to support Synopsys' DesignWare-® Mixed-Signal connectivity intellectual...

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C-Cores come in 32 sizes ranging from 5 VA to 5 kVA.

C-Cores come in 32 sizes ranging from 5 VA to 5 kVA.

Made from M5 silicon steel, C-Cores are suitable for single-phase transformers with single coils, both single loop and double loop, as well as double coil and double loop. They can be bobbin-wound and require no assembly or stacking of laminations. Rectangular tubes of phenolic or laminated paper required for winding cores are available for all sizes.

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IP Core supports PCIe specifications.

Incorporating technology for IP configuration and design verification, Databahn(TM) PCIe Core provides hardware developers with comprehensive, silicon-proven solution for deploying PCI Express technology. Dual-link, dual-mode core features 8-lane interface at physical layer. In single link mode, core may be configured as PCIe Endpoint or Root Complex. In dual-link mode, both links can be...

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DSP Cores suit converged mobile multimedia applications.

Utilizing OSEck RTOS, StarCore SC1000 and SC2000 provide high-speed control, signal processing, and media processing capabilities. Both families feature VLES instruction set to minimize power consumption. Software enables message-based LINX interprocess communications services, which facilitate design of complex mobile infrastructure applications spanning multiple DSP cores. OSEck delivers...

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Silicon IP Cores support AES/LRW and AES/GCM algorithms.

Starting at 30K ASIC gates and delivering up to 10 Gbps throughput, GLM1 and GLM2 enable System on Chip (SoC) vendors to build compact processors that support AES/LRW and AES/GCM cryptographic algorithms. Advanced Encryption Standard (AES) protects data in storage media as well as inside network, and both products support 128- and 256-bit keys. While GLM1 is designed for throughput of 12.8 Mbits...

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IP Bridge enables migration to AMBA 3 AXI protocol.

DesignWare-® Bridge Intellectual Property enables designers using serial PCI Express interface to interconnect system-on-chip (SoC) designs to migrate standard on-chip bus to AMBA 3 AXI protocol. Maintaining full bus bandwidth, bridge allows designers to add PCI Express external connectivity to their SoCs. Bridge results in networking, embedded, storage, and computer application designs capable...

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