Cores

PHY and SerDes IP Cores come in TSMC 65 nm G+ process.

Designed to promote performance in noisy digital ASICs, PCI Express(TM) PHY is intended for 2.5 and 5.0 Gbps operation and comes with PIPE standard interface, while SATA PHY meets SATA 1.5 and 3.0 Gbps as well as SAPIS interface standards. Also available, 1.0-5.0 Gbps multi-standard SerDes macro provides complete physical media attachment layer for PCI Express, SATA, SAS, and Fibre Channel serial...

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Ferrite Core Materials cover 10 kHz to 1 MHz frequencies.

Ferrite Core Materials cover 10 kHz to 1 MHz frequencies.

Featuring frequency range of 200 kHz to 1 MHz, F58 offers initial permeability of 750 when measured at 10 kHz and 0.1 mT. Ranging from 10 kHz to 500 kHz, P11 features initial permeability of 2,250 when measured at 10 kHz and 0.1 mT. Both manganese-zinc ferrite core materials are available in standard RM and pot cure geometries, while F58 is also available in toroidal core configuration....

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MotionDSP Announces Ikena Copyright, New Video Copyright Detection Technology

Patent-Pending Technology Works on Clips and Movies, Regardless of Format, Compression or Aspect Ratio March 13, 2006 - San Mateo, Calif. - MotionDSP, an emerging leader in digital video technology, today announced Ikena Copyright(TM), a copyright detection technology that matches content solely on the video content. Ikena Copyright uses a (patent-pending) component of MotionDSP's military-grade...

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Bluetooth IP Platform offers max transfer rate of 2.1 Mbps.

Optimizing data rate for stereo audio and multimedia file transfers, Bluetooth 2.0+EDR IP consists of complete hardware and software Bluetooth Baseband IP solution designed for embedded market. It provides full flexibility in choice of CPU, Bluetooth radio chipset, and operating system, offering customers range of system configurations when incorporating Bluetooth into their designs.

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IP Block targets video and graphics applications.

Silicon verified, 80 nm Line-Lock PLL IP Block uses digitally-programmable, low-jitter frequency synthesizer with high-resolution, 20-bit, noise shaping filter for fine-frequency tuning. Block has digital second loop and 2 programmable pixel clock outputs, and operates with pixel clocks up to 202.5 MHz. Occupying 0.55 mm2 of silicon, it dissipates 50 mW, with long-term peak-to-peak jitter of less...

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Synopsys IP for PCI Express 2.0 (Gen II) Passes PCI-SIG Compliance

First IP Provider to Pass PCI-SIG Compliance Testing With Complete PHY and Digital Controller Solution MOUNTAIN VIEW, Calif., Feb. 14 -- Synopsys, Inc. (NASDAQ:SNPS), a world leader in semiconductor design software, today announced that its DesignWare-® PHY and digital controller intellectual property (IP) for PCI Express(TM) 2.0 (Gen II) is the first complete Gen II IP solution from a single...

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Spreadtrum: New TD-SCDMA Core Chip Supporting HSDPA

BARCELONA, Spain, Feb. 13 // -- The first TD-SCDMA core chip (SC8800H), which supports HSDPA (High Speed Downlink Packet Access) function, has been recently developed by Spreadtrum Communications in Shanghai, China. With the HSDPA function, SC8800H can support high speed data download service so that not only the quality of traditional audio & video multimedia services can be highly improved, but...

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Scalable Graphics Core connects via PCI interface.

TES Display Controller/Accelerated Vector Engine (D/AVE) allows systems designers to integrate specific graphics functions, such as TFT pixel rendering, into Altera's Cyclone-® and Stratix-® series FPGAs. Suited for automotive and industrial display applications, this FPGA-based PCI graphics IP core generates vector graphics with sub-pixel processing and extended anti-aliasing functionality.

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eASIC and ASIC Architect Partner to Deliver New High-Speed PCI Express and DDR2 Interfaces for Nextreme Structured ASICs

ASIC Architect Join eASIC's Growing eZ-IP Alliance SANTA CLARA, Calif., Feb. 5 /- eASIC Corporation, a provider of Structured ASIC devices and Configurable logic IP, and ASIC Architect, a leading supplier of high speed IP cores, today announced the immediate availability of two new high-speed interfaces for eASIC's 90nm Nextreme Structured ASIC Family: PCI Express (PCIe) Endpoint Controller and...

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QNX Multi-Core Tools Deliver Comprehensive Debug and Optimization for P.A. Semi PWRficient Platform

OTTAWA, and SANTA CLARA, Calif., Feb. 5 /- QNX Software Systems, the industry leader in multi-core processing for embedded systems, and P.A. Semi, developer of the high-performance, low-power PWRficient(TM) processor family, announced today that the two companies will bring optimized multi-core development capability to the embedded market. The joint solution combines P.A. Semi's innovative ultra...

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Oilfield Improvements® Wheeled Rod Guide® Couplings Celebrate 35th Anniversary
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Oilfield Improvements® Wheeled Rod Guide® Couplings Celebrate 35th Anniversary

For over 35 years our Wheeled Rod Guide Couplings, have been at work in oil fields across the globe. Our products are engineered to extend the service life of sucker rods and tubing, delivering cutting-edge innovation that enhances oilfield operation, maximizes output, and enhancing overall operations. To learn about the advantages of using Wheeled Rod Guide Couplings in your wells, see our video.

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