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Cores

CompactFlash 4.1 Controllers enable high-speed storage.

Intended for digital photography and embedded applications, CompactFlash/CF+ IP Host and Device cores enable system designers and card manufacturers to build reliable memory and I/O CompactFlash systems. They comply with CF+ and CompactFlash-® Specification Revision 4.1. CompactFlash IP core supports standard transfer modes as well as advanced timing modes for memory and I/O access. IP supports...

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IP Core supports RapidIO® 2.1 specification.

Supporting up to 4 lanes at 5.0 GBaud per lane, Serial RapidIO IP Core addresses bandwidth needs of wireless and military markets. Core has been qualified against RapidIO Trade Association's bus functional model, is optimized for 40 nm Stratix-® IV FPGAs with embedded transceivers, and is supported within Quartus-® II software v9.1.

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Ethernet IP Cores feature IEEE 1588 PTP support.

Ethernet IP cores with IEEE 1588 enable distributed systems to select master clock among alternatives and compensate for network delay and jitter while keeping slave clocks tightly synchronized with master. IP cores can parse all standard IEEE 1588 frames and have hardware time-stamping for ingress and egress frames, and IP also includes timers and event synchronization blocks to generate...

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Configurable DSP IP Cores target RTAX-DSP space-flight FPGAs.

Configurable DSP IP cores enable designers to create common DSP functions such as filters and transforms for RTAX2000D and RTAX4000D DSP FPGAs. They use GUI embedded in Libero-® IDE and are supported through comprehensive software dialog windows that simplify selection and configuration of common DSP functions. Units can also generate structural netlists in either Verilog or VHDL and can be...

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Dataplane Core targets DSP applications.

Optimized for digital signal processing and control in system-on-chip dataplane, Xtensa LX3 DPU offers variety of pre-verified DSP options ranging from floating point accelerator to 16-MAC vector DSP. Base configuration can reach speeds over 1 GHz in 45 nm process technology with area of 0.044 mm-² and 0.015 mW/MHz power. When built with ConnX Baseband Engine DSP, Xtensa LX3 delivers over 10...

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Processor Cores offer 32-bit performance and 16-bit code.

Achieving performance of 1.5 DMIPS/MHz and 180 MHz in 130 nm, Model M14K(TM) is optimized for MCU and real-time embedded applications. It includes minimized interrupt latency, flash acceleration, debug features, and support for AHB Lite as interconnect interface. Based on MIPS32 4KEc(TM) micro-architecture, which provides Linux and Java engine, Model M14Kc(TM) has full cache controller and...

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PHY IP supports 28 nm processes in 1.8 V architecture.

Designed for smartphones, mobile Internet devices, and netbooks, DesignWare-® USB 2.0 picoPHY IP supports Battery Charging v1.1 specification, which allows mobile devices to draw up to 1.8 A of current when connected to wall charger. By supporting USB On-the-Go v2.0 specification, DesignWare USB 2.0 picoPHY incorporates Attached Detection Protocol feature, which optimizes power efficiency of...

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Dataplane Processor Core offers deeply embedded control.

Starting at size of 15,000 gates, 32-bit Xtensa 8 consumes less than 0.05 mm-² in 40 nm process technology with power dissipation starting at 10 -µW/MHz. Unit includes pairs of 32-bit GPIO, 32-bit Queue interfaces for direct connection to RTL blocks, and double-precision floating point accelerator option. Customizable device is suited for mobile phones and other portable electronic devices,...

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Transmit/Receive Controller supports HDMI.

Available in process technologies from 90 nm down to 40 nm, DesignWare HDMI(TM) transmitter and receiver digital controllers and PHY IP solution supports high-bandwidth digital content protection. It offers comprehensive set of IP deliverables that help designers embed complex interface into next generation multimedia SoCs. Solution includes optimized analog front end to support longer HDMI...

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PHY and Controller IP supports 1,866 and 2,133 Mbps data rates.

Supporting Low Voltage DDR3L specification that runs at 1.35 V, DesignWare-® DDR3/2 PHY and Digital Controller IP targets digital home, digital office, data center, and storage applications that require bandwidth in excess of 1,066 Mbps per pin. IP includes PHY Utility Block with built-in data training circuits to enable in-system calibration. As part of data training sequence, DDR3/2 IP...

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