Cores

Multi-Stream IP Cores target data networking applications.

Delivered as synthesizable Verilog RTL cores or as part of CebaFlex FPGA-based acceleration subsystems, CebaRIP Rapidly Tunable Silicon IP Cores are GZIP and GUNZIP IP cores capable of executing hundreds of thousands of data streams concurrently, without performance degradation. Devices offer context switching that saves state information on data packet boundaries, minimizing network latency....

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VLIW 8-MAC DSP Core accelerates data throughput.

Intended for SoC designs, ConnX 545CK dataplane processor core combines base CPU controller with DSP that can sustain 8 simultaneous MAC (multiply-accumulate) operations on independent data pairs per cycle utilizing 160-bit vector registers. It features 3-issue VLIW (very long instruction word) architecture with eight 16-bit multipliers that operate in SIMD mode. Capable of 600+ MHz operation,...

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Embedded Control Cores target high-performance applications.

Designed to facilitate SoC integration, Diamond Standard controllers include 5 upward-compatible processor cores based on common Xtensa architecture. These 32-bit embedded control cores, suited for embedded control functions in compute-intensive dataplane functions, are available as cache-enabled and cache-less controllers with on-chip debug hardware that achieves Dhrystone 2.1 results of...

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MIPI 4G DigRF-Compliant IP accelerates LTE/WiMAX SoC development.

DesignWare-® MIPI-® 4G DigRF(SM) Master Controller IP enables designers to lower risk of integrating DigRF interfaces into baseband ICs and application processors accelerating time-to-market of LTE and Mobile WiMAX SoCs. Compliant to MIPI DigRF v4 1.00 specification, controller implements features defined for protocol and PHY adaptation layers. Configurability of IP RTL provides flexibility for...

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DICOM-Compatible IP Core supports 8- and 12-bit JPEG.

Compact JPEG-E-X IP core supports both 8-bit Baseline and 12-bit Extended Sequential modes of JPEG image compression standard. Conformant to DICOM medical standard, unit compresses images from 8-12 bits per color sample, and also compresses non-standard motion JPEG streams. It can process 450 MS/sec with 69K gates in typical ASIC 0.09 micron process, 280 MS/sec in high-end FPGA devices, or 30 fps...

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MultiPHY IP supports 6 DDR standards.

MultiPHY IP supports 6 DDR standards.

DesignWare(TM) DDR multiPHY supports range of DDR SDRAM standards - LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L (1.35 V), DDR3U (1.2x V), DDR2 - in single PHY. This lets designers target different DDR types for single chip through software control, promoting flexible integration into various applications. Supporting data rates from 0-1,066 Mbps, product offers DFI 2.1-compliant interface to memory...

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SATA Device Controller IP includes CPU offloading capabilities.

Targeting 6 Gbps SSD applications, CEVA-SATA3.0 incorporates Native Command Queuing specifications for Isochronous data transfers and queue management, which in turn enables prioritized transfers of streaming audio and video data. Licensable RTP IP package is accompanied by complete set of deliverables, including comprehensive simulation environment, example C source code, and FPGA-based...

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Microcontroller IP Model Libraries support JTAG/Boundary Scan.

Structured modularly as intelligent IP, VarioTAP-® models for Microchip PIC32MX microcontrollers with MIPS(TM) Core enable complete fusion of boundary scan test and JTAG emulation. By employing this technology, on-chip Flash of PIC32MX types can be in-system programmed. Both embedded Flash and external Flash are supported. In addition, VarioTAP-® supports interlaced bus emulation tests and...

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Audio DSP Core targets home entertainment applications.

Featuring 32 x 24 multiply accumulator, HiFi EP is optimized for simultaneous multi-channel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products and Smartphones. To address requirements in mobile and VoIP applications, instructions have been added for noise cancellation and beam forming microphones. Cache memory subsystem includes predictive...

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Microprocessor Core target networking and storage SoCs.

Available on TSMC 40G process, PowerPC(TM) 476 operates at clock speeds in excess of 1.4 GHz, delivering 2.5 Dhrystone MIPS per MHz. Embedded DRAM block operates at up to 500 MHz, which is essential for real-time video processing and high-bandwidth networking applications. Processor core and memory block accelerate development of networking and storage SoCs used in applications such as...

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