Cores

Cores

FPGA-Based System enables wireless base station deployments.

Combining RapidIO MegaCore® Function IP core, implemented in Stratix® IV GX FPGA, with Serial RapidIO® Gen 2 switch from IDT, Serial RapidIO® Gen2 provides 20 Gbaud packet-based interconnect for linking radio cards, host processors, and digital signal processors in communications systems. Solution enables wireless customers, as well as those in military, medical, and...

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Cores

IP Core suits Video Over IP applications.

SMPTE 2022-5/-6 IP core accommodates needs of broadcast equipment developers delivering IP-based systems that transport raw, high-bit video from remote events to studios, post editing houses, and other points along production process. Offering Forward Error Correction (FEC) for video over IP, core lets developers build flexible, high-bandwidth systems capable of recovering IP packets lost to...

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Signal Processors

DSP Core features Dolby Mobile technology.

CEVA-TeakLite-III DSP implements 3rd generation Dolby® Mobile technology, including support of Dolby Digital Plus for mobile, for those designing mobile audio processors intended for portable devices. Used in mobile baseband and application processor chips, native 32-bit DSP core handles, among other tasks, mobile audio scenarios such as multi-stream audio playback with post-processing...

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Pipeline FFT Cores support data rates up to 52 GS/s.
Cores

Pipeline FFT Cores support data rates up to 52 GS/s.

Suited for real-time spectrum analysis over tens of GHz, HyperSpeed(TM) Plus Cores process complex data streams in continuous real-time at data rates in excess of 52 GS/s for 2,048 point FFT implemented on Xilinx Virtex-6 FPGA device. Bit-widths and internal memory partitioning are adjustable to meet user requirements. Cores are intended for applications requiring extreme processing speed within...

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Electronic Chips

IBM Unveils Cognitive Computing Chips

- IBM introduces first(1) computing core that combines digital "neurons" and on-chip "synapses" in working silicon. - Radical new compute core demonstrates synaptic plasticity, the foundation of learning and memory. - With no set programming, these cores mimic the event-driven, parallel processing abilities found in the brain. SAN JOSE, Calif., -- Today, IBM (NYSE: IBM) researchers unveiled a new...

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TAG® to Showcase Field-Upgradable CPU(TM) and Precision Guidance Technologies at the Joint Navigation Conference in Colorado Springs, Booth 42A
Personal Computers (PC)

TAG® to Showcase Field-Upgradable CPU(TM) and Precision Guidance Technologies at the Joint Navigation Conference in Colorado Springs, Booth 42A

TAG's Tactical Systems Division will be in Colorado Springs June 27th for a four-day military conference focused on technical advances in positioning, navigation and other precision guidance technologies. Colorado Springs, Colorado - Technology Advancement Group®, Inc. (TAG®) will be presenting their latest Field-Upgradable CPU and Precision Guidance Technologies at the annual Joint...

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Cores

LC Tank PLL IP targets high-end networking SoCs.

Achieving less than 300 fs-RMS random jitter performance, high-precision LC Tank PLL IP is intended for SoC applications running at data transfer rates of 100 Gbps and greater. It operates on less than 12 mW while providing multiphase clocks of up to 14 GHz in less than 0.26 mmÂ-² footprint. Silicon-proven in TSMC's 40 nm General Purpose (G) process, solution incorporates components such as...

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Cores

SerDes PHY IP Platform supports multiple standards.

Operating at speeds up to 12.5 Gbps and at 7.2 mW per Gbps of power per channel in quad configuration, MS PHY IP Platform supports 10GBase-KR, CEI-11G, PCIe 3.0, and SATA 6G standards. Device features digital control for programming SerDes, digital calibration and trimming, plus adaptation functionality that adjusts to varied channel characteristics. Low power transmit driver is immune to supply...

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Cores

LSI Now Shipping in Volume Second-Generation 40nm LDPC Read Channel for Hard Disk Drives

Low-density parity check (LDPC) iterative decoding read channel enables areal densities of 500GB per platter for 2.5-inch drives and 1TB per platter for 3.5-inch drives MILPITAS, Calif. -- LSI Corporation (NYSE: LSI) today announced it is shipping in volume the TrueStore® RC9700 read channel IP integrated into system-on-a-chip (SoC) designs for the hard disk drive (HDD) market. The...

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Solder Redefined
Sponsored

Solder Redefined

Indium Corporation has developed a new twist on traditional solder by developing a composite with a reinforced matrix internal structure. The result is a solder with increased strength and reliability. Check out this video to learn more about the mechanics behind the groundbreaking technology.

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