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Synopsys Unveils Industry's First Complete PCI Express 4.0 IP Solution

High-Quality DesignWare PHY, Controller and Verification IP for PCI Express Architecture Doubles Performance to 16 GT/s for Enterprise SoC Designs MOUNTAIN VIEW, Calif., -- Highlights: --Â-  Industry's first complete PCI Express® 4.0 IP solution, supporting the latest PCI Express 4.0 standard, will be featured on June 4(th) at the PCI-SIG® Developers Conference 2014 in Santa...

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Miscellaneous Controllers

Cadence Offers Production Proven USB 3.0 Host Controller IP

USB Design IP is Used in Industry Standard Compliance Program SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that a production proven host controller intellectual property (IP) for USB 3.0 has been added to the Cadence IP offering. The CadenceÂ-® USB 3.0 xHCI host controller IP was originally developed by Fresco...

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Programmable Logic Controllers

Xilinx Highlights All Programmable and Smarter Vision Solutions at Embedded Vision Summit West 2014

SAN JOSE, Calif. - Xilinx, Inc. (NASDAQ: XLNX), will highlight its All Programmable and Smarter Vision solutions at the Embedded Vision Summit West, May 29, 2014 in Santa Clara, CA.-  Xilinx technology experts will present and demonstrate Xilinx's capabilities and solutions portfolio for smarter embedded vision systems. Xilinx® All Programmable devices, coupled with Xilinx's...

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Programmable Logic Controllers

Xilinx Highlights All Programmable and Smarter Vision Solutions at Embedded Vision Summit West 2014

SAN JOSE, Calif. - Xilinx, Inc. (NASDAQ: XLNX), will highlight its All Programmable and Smarter Vision solutions at the Embedded Vision Summit West, May 29, 2014 in Santa Clara, CA.Â-  Xilinx technology experts will present and demonstrate Xilinx's capabilities and solutions portfolio for smarter embedded vision systems. Xilinx® All Programmable devices, coupled with Xilinx's...

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Cores

Casa Systems and Teleste Collaborate to Bring Multigigabit Subscriber Speeds to the Cable Access Network

TURKU, Finland and ANDOVER, Massachusetts – Companies are targeting to launch a next generation, DOCSIS 3.1 and CCAP compliant, distributed architecture (RemotePHY) solution Teleste, a leading provider of video and broadband technologies and services [http://www.teleste.com, and Casa Systems, a worldwide leader in next-generation cable edge technology and an innovator of converged fixed-mobile...

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Cores

Casa Systems and Teleste Collaborate to Bring Multigigabit Subscriber Speeds to the Cable Access Network

TURKU, Finland and ANDOVER, Massachusetts – Companies are targeting to launch a next generation, DOCSIS 3.1 and CCAP compliant, distributed architecture (RemotePHY) solution Teleste, a leading provider of video and broadband technologies and services [http://www.teleste.com, and Casa Systems, a worldwide leader in next-generation cable edge technology and an innovator of converged fixed-mobile...

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Cores

DDR4 PHY IP targets microserver market.

Built on 16 nm FinFET process, Cadence-® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers realize...

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Cores

DDR4 PHY IP targets microserver market.

Built on 16 nm FinFET process, CadenceÂ-® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers...

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Cores

Cadence Announces Immediate Availability of Industry's First Verification IP for PCI Express 4.0 Technology

Support for next-generation PCI Express architecture enables faster completion of functional verification of SoC designs SAN JOSE, Calif. -- Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced the availability of the industry's first verification IP (VIP) supporting PCI Express-® (PCIe®) 4.0 architecture. This VIP enables designers to quickly and...

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Cores

Cadence Announces Immediate Availability of Industry's First Verification IP for PCI Express 4.0 Technology

Support for next-generation PCI Express architecture enables faster completion of functional verification of SoC designs SAN JOSE, Calif. -- Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced the availability of the industry's first verification IP (VIP) supporting PCI ExpressÂ-® (PCIe®) 4.0 architecture. This VIP enables designers to quickly...

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