TI Makes Programming in Real Time as Easy as 1-2-3
Introducing expanded PRU software support and the first PRU cape plug-in board for BeagleBone Black from TI DALLAS- – The programmable real-time unit (PRU) on Sitara™ processors from Texas Instruments (TI) (NASDAQ: TXN) enables customers to differentiate their products by offloading real-time processing from the ARM® core. The PRU is a 200MHz low-latency multicore co-processor optimized...
Read More »TI Makes Programming in Real Time as Easy as 1-2-3
Introducing expanded PRU software support and the first PRU cape plug-in board for BeagleBone Black from TI DALLASÂ- – The programmable real-time unit (PRU) on Sitara™ processors from Texas Instruments (TI) (NASDAQ: TXN) enables customers to differentiate their products by offloading real-time processing from the ARM® core. The PRU is a 200MHz low-latency multicore co-processor...
Read More »Easy Testing and Programming of Texas Instruments TM4Cxx Microcontrollers with VarioTAP®
Universal processor emulation with VarioTAP-® technology by GOEPEL electronics is now available for the Tiva™ C series from Texas Instruments. The processor is reconfigured to provide design-integrated test and programming instruments via the native debug port. A respective VarioTAP® model, as part of an extensive IP library, contains all relevant access information for the respective...
Read More »Easy Testing and Programming of Texas Instruments TM4Cxx Microcontrollers with VarioTAP-®
Universal processor emulation with VarioTAPÂ-® technology by GOEPEL electronics is now available for the Tiva™ C series from Texas Instruments. The processor is reconfigured to provide design-integrated test and programming instruments via the native debug port. A respective VarioTAP® model, as part of an extensive IP library, contains all relevant access information for the...
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Quick Release & Spring Loaded Pins - Fast, Convenient and Secure
To learn more about the different types of pins available or which ones to select for your specific application, download our product guide.
Read More »Verification IP supports all popular 3D memory standards.
Supporting Wide I/O 2, HMC, HBM, and DDR4-3DS Standards, Verification IP enables designers to accelerate verification of memory interfaces and achieve system-on-chip verification closure for compute server applications, mobile devices, high-performance graphics, and network applications. Advanced features include direct memory access for read, write, save, preload, and comparison of memory...
Read More »Verification IP supports all popular 3D memory standards.
Supporting Wide I/O 2, HMC, HBM, and DDR4-3DS Standards, Verification IP enables designers to accelerate verification of memory interfaces and achieve system-on-chip verification closure for compute server applications, mobile devices, high-performance graphics, and network applications. Advanced features include direct memory access for read, write, save, preload, and comparison of memory...
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Low-Power IP Core targets multi-core implementations.
Based on Cortus v2 instruction set, Model APS25 supports accelerating computation through using coprocessors or symmetric multiprocessing and can serve as building block in dual- or multi-core systems. Cortus v2 instruction set allows seamless mixing of 16-, 24-, and 32-bit instructions without mode switching. Featuring Harvard architecture, core provides sixteen 32-bit registers, 5-stage...
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Low-Power IP Core targets Internet of Things applications.
Based on Cortus v2 instruction set, Model APS23 is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart. Cortus v2 instruction set allows seamless mixing of 16-, 24-, and 32-bit instructions without mode switching. Featuring Harvard architecture, core has sixteen 32-bit registers, 3-stage pipeline, and sequential multiplier....
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Low-Power IP Core targets multi-core implementations.
Based on Cortus v2 instruction set, Model APS25 supports accelerating computation through using coprocessors or symmetric multiprocessing and can serve as building block in dual- or multi-core systems. Cortus v2 instruction set allows seamless mixing of 16-, 24-, and 32-bit instructions without mode switching. Featuring Harvard architecture, core provides sixteen 32-bit registers, 5-stage...
Read More »
Low-Power IP Core targets Internet of Things applications.
Based on Cortus v2 instruction set, Model APS23 is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart. Cortus v2 instruction set allows seamless mixing of 16-, 24-, and 32-bit instructions without mode switching. Featuring Harvard architecture, core has sixteen 32-bit registers, 3-stage pipeline, and sequential multiplier....
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Simple Connection – MGB with EtherNet/IP
The new MGB with EtherNet/IP is a leap forward in access door safety. Designed for easy installation, flawless performance, and long service life, it is engineered with robust features and cutting-edge technology that places it firmly at the leading edge of the door safety device industry. To learn all about the benefits of the Euchner MGB, see our video.
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