Cores

Microsemi's SmartFusion2 SoC FPGAs and IGLOO2 FPGAs Security Technology Recognized for Securing the Internet of Things (IoT) as One of the Top Nine Technologies at Electronica by EE Times

SmartFusion2 SoC FPGAs and IGLOO2 FPGAs Solutions Offering Secures Machine-to-machine Connections From the Node to the Cloud in the Internet of Things ALISO VIEJO, Calif. - Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced its SmartFusion2-® SoC FPGAs and IGLOO2-® FPGAs Securing the...

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SMIC Successfully Produces Qualcomm Snapdragon 410 Processor in 28nm Process

SHANGHAI- – Semiconductor Manufacturing International Corporation (SMIC; NYSE: SMI; SEHK: 981) and Qualcomm Incorporated (NASDAQ: QCOM) today announced that its subsidiary, Qualcomm Technologies, Inc., and SMIC have achieved a major milestone in fabrication of 28nm Qualcomm-® Snapdragon™ 410 processors. This milestone comes six months after SMIC and Qualcomm Technologies announced their...

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Verification IP targets low-power memory controllers.

Based on 100% native SystemVerilog Universal Verification Methodology architecture, Synopsys VIP for LPDDR4 comes with verification plans, built-in coverage, and protocol-aware memory debug environment. Transactor and monitor functions provide set of protocol, methodology, verification, and productivity features, enabling users to achieve rapid verification convergence on LPDDR4-based designs....

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Verification IP supports PCIe 4.0.

With design-aware Mentor-® EZ-VIP PCI Express Verification IP, engineers can- reduce time spent building test benches for ASIC and FPGA design verification. PCIe EZ-VIP includes pre-packaged verification environments for serial and parallel interfaces of PCIe 1.0, 2.0, 3.0, 4.0, and mPCIe, which can be used to verify PHY, Root Complex, and Endpoint designs. Test plans, compliance tests, test...

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Encoder IP Core features dual-format design.

Implementing HEVC/H.265 and AVC/H.264 video compression formats, Dual-Format Encoder IP Core- is suitable for any video encoding application. Key technical advantage of solution is optimized integration of both standards using minimum logic and memory resources within single IP. Adaptable to maximum resolution supported by target application, ranging from HD to UHD/4K,- IP is suited for...

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Microsemi Announces Collaboration with New Wave DV to Develop Innovative Networking Products and IP Cores for Ethernet and Fibre Channel Solutions

New Secure 4-Port Networking PMC/XMC Card and Fibre Channel IP Core with SmartFusion2 SoC FPGAs and IGLOO2 FPGAs Allow Faster Development Cycles for a Wide Range of Applications ALISO VIEJO, Calif. - Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced its collaboration with New Wave...

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Barco Silex' FIPS-compliant DRBG IP Integrated in Innovative Short-range Wireless ICs of Dialog Semiconductors

Louvain-la-Neuve, Belgium –- Barco Silex, a leading provider of cryptography IP cores, today announced that Dialog Semiconductor, the provider of smart wireless solutions, successfully integrated the Barco Silex BA431 IP core into its short range wireless communication ASIC. This core is a FIPS-140-2-certified deterministic random bit generator (DRGB) combined with a True Random Generator...

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Altera to Exhibit Comprehensive Solution Portfolio for Accelerating Intelligent Automation at SPS IPC Drives 2014

Demos Include Secure Cloud-Enabled PLC for IoT and Industry 4.0, Precision Robotics, Motor Control and IEC61508 Functional Safety San Jose, Calif. –- Altera Corporation (NASDAQ: ALTR) today announced that it will demonstrate industrial solutions based on its field-programmable gate arrays (FPGAs) and SoCs at the SPS IPC Drives conference in Nuremberg, Germany, from November 25 to 27. Altera...

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IP Core fosters development with Altera Cyclone V FPGAs/SoCs.

Available for Sercos III master and slave controllers (SERCON100M/S), Sercos-® III IP Core includes all hardware functions, such as timing, synchronization, and processing of cyclic and non-cyclic data, on basis of- 2 integrated Ethernet MACs. Sercos III master and slave devices can be implemented as single-chip solution using Altera Cyclone-® V FPGAs or SoCs, which integrate ARM-® dual-core...

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