Tunable Downconverter IP Core boosts channel density.

Pentek Sep 07, 2005

Press Release Summary:

Designed for Xilinx's Virtex II, Virtex II Pro, or Virtex 4 FPGAs, 256-channel Model 4954-430 handles 16-bit real or complex input data at up to 185 MHz. Channelizer stage generates 1,024 fixed adjacent frequency channels with alias-free performance greater than 75 dB across passband of each channel. Each of 256 DDCs has programmable numerically controlled oscillator to implement independent fine-tuning for each channel, and mixer to translate signal of interest to baseband.

Original Press Release:

Pentek's Tunable Downconverter IP Core Boosts Channel Density by Order of Magnitude for Military Radios and Commercial Wireless

- 256-Channel Narrowband Digital Downconverter Core Now Part of Pentek's GateFlow IP Library for FPGAs - Programmable Number of Individually Tunable Output Channels - Handles 16-Bit Real or Complex Input Data at Rates up to 185 MHz UPPER SADDLE RIVER, NJ-August 24, 2005-Pentek, Inc., announced today an addition to its GateFlow FPGA IP Library that implements a 256-channel narrowband digital downconverter (DDC). Designed for use in Xilinx's Virtex II, Virtex II Pro or Virtex 4 FPGAs, the Model 4954-430 core utilizes a unique architecture to achieve 64 times the channel capacity of conventional quad ASIC downconverters. This intellectual property (IP) core is ideal for developers of applications requiring a high number of digital downconverter channels with size, weight, cost and power constraints, such as military radios and commercial wireless. "This represents a huge boost in channel density," says Rodger Hosking, vice president of Pentek, Inc. "In the past we have been limited to just a handful of DDC channels in a single device. The Model 4954-430 core delivers an extremely high channel-to-FPGA ratio, with density at least an order of magnitude higher than any other implementation available in either FPGA or ASIC form." Accepting real or complex data samples at rates up to 185 MHz, the architecture utilizes a channelizer stage that generates 1024 fixed adjacent frequency channels with alias-free performance greater than 75 dB across the passband of each channel. A 256-output switch matrix follows the channelizer, providing a coarse tuning capability for the desired output channels. Each of the 256 DDCs has a programmable numerically controlled oscillator (NCO) to implement independent fine-tuning for each channel and mixer to translate the signal of interest to baseband. A decimating FIR low-pass filter then defines the channel bandwidth of the baseband output. The NCOs have a frequency resolution of 32-bits, and the baseband outputs pass through a programmable gain stage before being rounded to their final 16-bit result. Each channel has an independently programmable 16-bit gain control. The decimation factor setting is common to all channels and is programmable from 1024 to 9984 in steps of 256. Decimation filter coefficients are user-programmable in RAM structures, and a complete set of factory-default values are supplied for an 80 percent passband response filter for all 35 decimation factors. For an input sample rate of 185 MHz, the resulting output bandwidth ranges from approximately 14.8 kHz to 144 kHz. Flexible Tuning-Independent Channels The Model 4954-430 accepts 16-bit input real or complex data and generates 256 independently tunable 16-bit complex output channels. The core offers extremely fine tuning capability with 32-bit tuning resolution per channel. Pentek's GateFlow FPGA Resources Pentek's three-fold GateFlow FPGA Resources comprise the GateFlow FPGA Design Kit. The kit supports user-developed FPGA code; the GateFlow IP Core Libraries including high-performance DDCs as the 4953-430; Fast Fourier Transforms (FFTs) and radar pulse compression algorithms; and the GateFlow Factory Installed IP Cores. This allows customers to take immediate advantage of FPGA technology with zero FPGA development effort. Pricing and Availability The Model 4954-430 IP is priced at $14,995 with delivery from eight to 10 weeks ARO. To simplify the acquisition process, Pentek's GateFlow IP Core Libraries are offered under the standardized SignOnce IP Project License, the industry's first multi-vendor common license for FPGA-based IP. The core is also available as a factory-installed option on several of Pentek's FPGA boards. About Pentek Pentek develops, manufactures and markets innovative DSP systems to original equipment manufacturers, distributors and value-added resellers. Pentek offers powerful VME, PMC, VIM and PCI boards for data acquisition, software radio and digital signal processing featuring Texas Instrument's C6000 DSPs, Motorola's G4 PowerPC and Xilinx FPGAs. Pentek's I/O includes A/Ds, D/As, digital downconverters and upconverters and more. Pentek equips products with interfaces including XMC, VXS and FPDP-II and offers strong DSP software support. Pentek and GateFlow are registered trademarks of Pentek, Inc. Brand or product names are registered trademarks or trademarks of their respective holders. North American Sales Contact: Mario Schiavone, Pentek, Inc., One Park Way, Upper Saddle River, NJ 07458-2311; telephone 201-818-5900, ext. 762; fax 201-818-5904; email news@pentek.com, website www.pentek.com. International Sales Contacts: Please visit www.pentek.com/contact/replist.pdf for a full list of international Pentek representatives and distributors.