Synchronous DDR PHY Technology achieves GHz clock rates.
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Press Release Summary:
Offering configurability needed to satisfy physical implementation requirements, phase PHY technology for DDR SDRAM physical interfaces delivers memory system performance up to 1,066 MHz clock speeds on 65 nm foundry process nodes or lower. Oversampling architecture employs 8- or 16-phase lock loop and performs pattern matching to determine correct data sample points for DDR data for each transaction. Also, differences in routing of data and data strobe signals are calibrated in silicon.
Original Press Release:
Denali Announces State-of-the-Art GHz DDR PHY Technology
Advanced Phase PHY Incorporates An Innovative Over-Sampling Approach Achieving Rapid Implementation Times for High-Performance Memory Systems
SUNNYVALE, Calif. -- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower. Denali's phase PHY technology applies a high-speed oversampling architecture paired with per-bit data capture and calibration mechanism to achieve GHz clock rates. This third-generation DDR PHY technology is delivered as a fully-synchronous design which benefits design teams with the configurability needed to satisfy their physical implementation requirements.
As DDR SDRAM devices reach 2133 Mbps data rates, bit-to-bit skews within the data lanes become significant fractions of the data window. Denali's oversampling architecture employs an 8- or 16-phase lock loop (PLL) and performs pattern matching to determine the correct data sample points for DDR data for each transaction. By managing the data capture on a per-bit basis (rather than on a per-byte basis), Denali's PHY reliably closes timing at 1066 MHz clock rates. Furthermore, differences in the routing of data and data strobe signals are calibrated in the silicon eliminating the need for time-consuming hand layout. The fully-synchronous design provides flexibility for floorplanning, pin placement, and power routing and uses standard EDA toolsets to easily realize a reliable implementation.
"The continued demand for increased bandwidth in various internet and electronic applications is driving the need for DDR3 technology and for the ability to support data rates up to 2133 Mbp/s," states Mike McKeon, director of PHY IP at Denali. "Our DDR phase PHY is cutting-edge technology, delivering effective management of GHz clock speeds and a perfect match for our customers' specific design implementation needs."
About Databahn DDR PHY Solutions
Denali's Databahn DDR PHY is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer's DDR application. The PHY is configurable for data width, ECC, low power, and many other options, and supports DDR3/2 and LP-DDR1/2 devices. For more info, visit: denali.com/ddrphy, Databahn PHY Frequently Asked Questions, and Animated Guide to Denali DDR PHY.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, USB, NAND Flash and DDR SDRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at denali.com.
Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.
