Synchronizer suits ATCA, AMC, and MicroTCA applications.

Press Release Summary:

Single-chip ZL30117 is capable of generating less than 1 ps rms of jitter in full compliance with OC-48 and STM-16 requirements. Adaptable unit, which consumes under 0.9 W of power, accepts 3 reference inputs - supporting clock frequencies in any multiple of 8 kHz up to 77.76 MHz as well as 2 kHz. Holdover capability enables it to ride out complete loss of incoming reference; PLL continues to operate in full compliance with network requirements for several seconds.

Original Press Release:

Zarlink Introduces Carrier-Class Synchronization Chip for AdvancedTCA, AMC and MicroTCA Applications

OTTAWA, Feb. 9 / -- Zarlink Semiconductor (NYSE/TSX:ZL) today launched a single-chip, ultra-low jitter synchronizer that solves the timing challenges posed by the popular AdvancedTCA (telecommunications computing architecture), AMC (advanced mezzanine card) and MicroTCA architectures. Feature rich and highly integrated, Adding 90 International Properties to its Hotel ProgramZL30117 chip meets or exceeds international standards and is the smallest and lowest power synchronizer for open-platform telecom architectures.

ATCA is gaining acceptance as an open architecture for adaptable, modular design in next-generation communications equipment. AMC is an open specification for mezzanine cards optimized for, but not limited to, ATCA applications. MicroTCA is a cost-optimized architecture that uses AMCs that are plugged directly into backplanes. By using standard hardware and software components from multiple vendors, ATCA, AMC, and MicroTCA reduce the time and cost-to-market of high-performance, high-density systems, but present challenges for achieving carrier-grade synchronization reliability.

"Zarlink is focusing its expertise in clock generation and network synchronization to overcome the timing issues posed by ATCA, AMC and MicroTCA designs," said Louise Gaulin, product line director, Zarlink Semiconductor. "Backed by our applications and systems design experience, the ZL30117 PLL ensures compliance with all major telecom standards and gives equipment designers the carrier-grade timing reliability they need for next-generation designs."

ATCA, AMC and MicroTCA are ideal for telecom applications, including 3G wireless mobile infrastructures and wireline equipment such as media gateways and MSPPs (multi-service provisioning platforms). Research indicates that the market for the commercial building blocks of ATCA equipment alone will grow from almost zero in the early 2000s to US$3.7 billion by 2007. Network equipment vendors are currently evaluating Zarlink's new PLL for their next-generation designs.

Optimized for Advanced Mezzanine Cards

The ZL30117 synchronizer offers robust features for AMCs used in ATCA and MicroTCA designs. While easy to use and adaptable, AMCs do not provide redundant timing reference inputs to support carrier-grade timing. The holdover capability of the ZL30117 chip enables it to ride out the complete loss of its incoming reference, which can occur when switching from a failed clock unit to a backup clock unit. The ZL30117 PLL continues to operate in full compliance with network requirements for several seconds after losing its reference, allowing time for the system to provide another reference source to the AMC.

The ZL30117device accepts three reference inputs, supporting clock frequencies in any multiple of 8 kHz up to 77.76 MHz, as well as supporting 2 kHz. The ZL30117 can directly lock to any of the standard clock input frequencies available to an AMC in an ATCA or MicroTCA application.

New PLL Expands Low-Jitter Synchronization Platform

The ZL30117 device is the newest in Zarlink's family of synchronization chips. The ZL30116 and ZL30119 devices, introduced in December 2005, are the industry's smallest programmable digital/analog PLLs for system and line card synchronization in SONET/SDH MSPPs and multi-service edge products. Only Zarlink's devices combine the capabilities to lock to 8kHz references, smoothly switch between references and generate ultra-low jitter clocks.

Most digital PLLs generate too much jitter for interfaces at rates above OC-3, necessitating a separate analog PLL to "clean up" the noise. Multi-chip combinations or modules may be as large as one square inch. Zarlink is first to deliver a single-chip synchronizer capable of generating less than 1 picosecond RMS (root mean square) of jitter in full compliance with OC-48 and STM-16 requirements. The ZL30117 PLL consumes less than 0.9 Watts of power and measures just 9 x 9 mm.


The ZL30117 PLL is available now. For information, visit: For more information on Zarlink's complete timing portfolio, visit:

About Zarlink Semiconductor

For over 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The Company's success is built on its technology strengths including voice and data networks, optoelectronics and ultra low-power communications. For more information, visit

Shareholders and other individuals wishing to receive, free of charge, copies of the reports filed with the U.S. Securities and Exchange Commission and Regulatory Authorities, should visit the Company's web site at or contact investor relations.

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