Press Release Summary:
While CEVA XS-1100A is optimized for wireless baseband applications, and CEVA XS-1200A is aimed at multimedia and other applications requiring high-performance signal processing, both configurable hardware platforms offer verified approach for integrating CEVA-X DSP cores into complex system on chips (SoCs). Use of industry-standard system buses enables designers to add their own hardware blocks or connect DSP to other systems present on chip.
Original Press Release:
CEVA Unveils High-Performance, Low Power Platforms for Wireless, Multimedia Applications
Highly integrated configurable subsystem for rapid design of CEVA-X DSP based System-on-Chips; Optimized for speed, power and die size requirements of next-generation communications and multimedia devices
SAN JOSE, Calif., April 21 -- CEVA, Inc. (NASDAQ:CEVA); , a leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today announced its next generation DSP subsystem platforms for developers using the CEVA-X family of DSP cores. The robust solutions build on CEVA's extensive track record of powering complex, multi-function communications products and offer a comprehensive and verified approach for efficiently integrating its cores into complex system on chips (SoCs). The platforms come in two versions, the CEVA XS-1100A optimized for wireless baseband applications, and the CEVA XS-1200A aimed at multimedia and other applications requiring high-performance signal processing.
These configurable, highly efficient hardware platforms reduce development effort, the risk of costly silicon re-spins and, ultimately, time-to-market for embedded processor applications. It uses industry standard system buses, offering designers the ability to add their own hardware blocks or connect the DSP to other systems present on chip, making integrating CEVA cores a very straightforward, efficient proposition. Both platforms support critical low power design requirements through CEVA's smart Power Management Unit (PMU) technology, which includes automatic sleep/wake of each resource and matrix separately according to transaction type, source, destination, initiator and duration.
"Our customers compete in some of the most dynamic and fastest moving markets and need every advantage possible to reduce time, risk and development complexity. These enhanced platforms build on our track record of expertise in wireless and multimedia, and provide an extremely effective way to leverage the capabilities of our family of DSP cores into complete systems," said Eran Briman, vice president, corporate marketing at CEVA. "More than 90% of our CEVA-X DSP core customers also license a complementary CEVA subsystem, illustrating the critical value-add that these platforms bring to developing complex processor-based solutions."
The two platforms -- which have evolved through numerous customer engagements in targeted application areas -- feature architecture enhancements that can significantly lower die size and power consumption, without compromising on performance. They are geared for the most complex and highly integrated SoCs, and feature a complete AHB matrix, DMA, TDM ports, power management, external master and slave ports, complete lineup of DSP-oriented peripherals and interface to L2 memories.
Compared to previous generation platforms from CEVA, the new platforms offers designers the following advantages:
-- 10% higher speed
-- 20% smaller die size
-- 20% lower leakage power and 10% lower dynamic power
-- 50% fewer clock-tree cells, ensuring higher production yield
-- 5% decrease in MHz requirements for video codecs such as H.264
The CEVA XS1100A platform is optimized for wireless baseband and general purpose DSP solutions and tightly couples the CPU and DSP, which is required for real time baseband processing. It includes the following main features:
-- Smart Power Management Unit (PMU) for dynamic control of power consumption
-- Complete set of hardware peripherals extendible through an APB bridge
-- Host controller connectivity through AHB compliant bridges
-- Two-level memory architecture enabling shared memory between CEVA DSP and ARM cores, reducing system complexity, die size and power consumption
-- Code replacement unit enabling on-the-fly firmware program bypasses
The CEVA XS1200A platform, aimed at multimedia and other DSP-intensive applications, enables a de-coupling of the CPU and DSP to support multiple independent clock systems. It integrates additional features that enhance the system processing power for applications such as digital multimedia devices and includes:
-- A 16-channel advanced DMA with 3D transfer capabilities, allowing the DSP to handle most of the data traffic autonomously
-- An interface to third-party accelerators that can be used for DSP-intensive applications
-- Up to 4 TDM ports for use as the interface to audio and voice data
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is a leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores for mobile handsets, consumer electronics and storage applications. CEVA's IP portfolio includes comprehensive solutions for multimedia, audio, voice over packet (VoP), Bluetooth and Serial ATA (SATA), and a wide range of programmable DSP cores and subsystems with different price/performance metrics serving multiple markets. In 2007, CEVA's IP was shipped in over 225 million devices. For more information, visit http://www.ceva-dsp.com/
CONTACT: Richard Kingston of CEVA, Inc., +1-408-514-2976, firstname.lastname@example.org