Software supports Stratix II FPGA design.
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Press Release Summary:
Quartus II v4.0 features TCL scripting interface, which lets designers mix-and-match between GUI and scripting design techniques. Memory compiler waveform generator graphically supports what-if analysis by producing waveform displays of memory structure operation. SOPC Builder tool supports IP-based design without requiring lower-level HDL or schematics. Software offers multi-clock timing analysis, integrated power analysis, and chip editor.
Original Press Release:
Altera's Quartus II Version 4.0 Software Delivers Most Advanced Technology for High-Density FPGA Design
Quartus II Version 4.0 Software Supports Stratix II Devices, the Industry's Biggest and Fastest FPGAs
San Jose, Calif., February 3, 2004--Altera Corporation (NASDAQ: ALTR) today announced that its Quartus® II version 4.0 design software is now shipping with full support for its new Stratix(TM) II FPGAs, which deliver more than twice the density and 50 percent higher performance compared to the first-generation Stratix family. The Quartus II software allows designers to tap the full potential of the Stratix II device family by handing them the most advanced technology available for high-density FPGA design. With the industry's easiest-to-use design flow methodology, system design capability, timing closure, and verification solution, this new version of Quartus II software delivers the most advanced development environment for FPGA design.
"In addition to providing the most advanced FPGA features, Altera is also on the leading edge with its development tools, and as a result, Quartus II software is the most powerful and easy-to-use FPGA software on the planet," said Perry J. Brown, President, Odyssey Technologies. "Here at Odyssey, we specialize in the design and development of leading-edge sophisticated communications systems, and time-to-market is always critical, which is why we rely on Altera's FPGAs and Quartus II software."
"Software innovation and technology leadership are Altera's heritage, and the release of this Quartus II software continues this tradition. We're seeing confirmation of our leadership in the marketplace," said Tim Southgate, vice president of software and tools marketing at Altera. "The number of active Quartus II software seats has now grown for nine consecutive quarters because customers recognize that Altera's software technology leadership consistently translates into superior ease-of-use and faster time-to-market."
Design Flow Methodology Leadership
Quartus II version 4.0 software, combined with technologies from Altera's EDA partners, delivers the industry's most advanced design methodologies for high-density FPGAs. Altera's Quartus II software is the only design environment that allows designers to target both FPGAs and structured ASICs seamlessly. With Altera's LogicLock(TM) methodology, Quartus II software is the pre-eminent FPGA design tool to deliver a true block-based design flow, providing unrivaled support for team-based designs. Furthermore, Altera's Quartus II software is the only FPGA design tool that offers an industry-standard TCL scripting interface, allowing designers to mix-and-match between GUI and scripting design techniques. This new version of Quartus II software further accelerates design with a new memory compiler waveform generator that graphically supports 'what if' analysis by dynamically producing waveform displays of memory structure operation based on user parameterization.
System Design Leadership
Altera's software development leadership is particularly evident in support for system-level design. The SOPC Builder tool within Quartus II design software is the programmable logic device (PLD) industry's only tool to support intellectual property (IP)-based design, including complete and automated system definition and implementation, without requiring lower-level HDL or schematics. SOPC Builder leverages the extensive collection of IP from Altera and its Altera Megafunction Partners Program (AMPPSM) members to provide a rich set of application-specific IP for rapid incorporation into a system-level design. With this version of Quartus II software, SOPC Builder extends its leadership position with improved support for multiprocessor systems and faster system generation.
Timing Closure Technology Leadership
Quartus II software delivers the most comprehensive set of timing closure technologies in the FPGA industry. With the FPGA industry's only integrated physical synthesis technology; the new RTL Viewer, the most powerful array of graphical analysis tools; Design Space Explorer, the industry's only automated performance optimization tool; and an incremental fitting technology, Quartus II software delivers unmatched capability for designers to choose from highly automated or "power user" methods to reach aggressive goals for performance and area. Additionally, advancements to the core place and route technology in Quartus II version 4.0 deliver, on average, 50 percent better Fmax performance and 18 percent faster compile times when comparing designs targeting the new Stratix II FPGAs to the original Stratix FPGAs. Also, when comparing version 4.0 to version 3.0, users can save up to 50 percent compile time across all Altera PLD families when using the timing-driven enhancements contained in the new Auto Fit option.
Leadership in Verification Solutions
In addition to integrating with all of the leading third-party EDA verification tools and methodologies, Quartus II software provides advanced multi-clock timing analysis capabilities, integrated power analysis, a chip editor to implement design changes in system in just minutes, and the SignalTap® II embedded logic analyzer. The SignalTap II embedded logic analyzer supports the most channels, fastest clock speeds, largest sample depths available, and, with Quartus II version 4.0 design software, now features the most advanced triggering capabilities available in an FPGA embedded logic analyzer.
Pricing and Availability
Quartus II version 4.0 design software is now shipping to all customers with an active software subscription. The annual subscription for the Altera design software is $2,000 for a node-locked PC license. Altera's software subscription program simplifies the process of obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Quartus II design software supports major operating systems, including Windows XP, Windows 2000, Windows NT, Sun Solaris, Red Hat Linux, and HP-UX.
New or existing customers may obtain a software subscription on line on the Altera web site, www.altera.com, or from Altera distributors worldwide. Free Quartus II Web Edition software is available from the Altera web site at www.altera.com/q2webedition and from the free Quartus II Software Starter Suite CD.
About the Stratix II Device Family
Stratix II FPGAs are the industry's biggest and fastest FPGAs. Developed with an innovative new logic structure, Stratix II devices offer over twice the logic density and 50 percent higher performance at 40 percent lower cost than first-generation Stratix devices. The Stratix II FPGA family is built on TSMC's 90-nm, all-copper process, using low-k dielectric material on 300-mm wafers. The new logic structure allows designers to conserve device resources by packing more functionality into a smaller area. For more information about Stratix II devices, please visit www.altera.com/stratix2.
About Altera
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.
