Silicon IP Cores support AES/LRW and AES/GCM algorithms.
Press Release Summary:
Starting at 30K ASIC gates and delivering up to 10 Gbps throughput, GLM1 and GLM2 enable System on Chip (SoC) vendors to build compact processors that support AES/LRW and AES/GCM cryptographic algorithms. Advanced Encryption Standard (AES) protects data in storage media as well as inside network, and both products support 128- and 256-bit keys. While GLM1 is designed for throughput of 12.8 Mbits per MHz, GLM2 delivers 25.6 Mbits per MHz.
Original Press Release:
IP Cores, Inc. Announces Two New Multi-Gigabit IP Combo AES/LRW and AES/GCM Cores for System on Chip (SoC) Design
IP Cores, Inc. announces two silicon IP cores supporting new industry standards. Starting at 30K ASIC gates and delivering up to 10 Gbps throughput, GLM1 and GLM2 cores provide a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage or IEEE 802.1AE networking solution.
Palo Alto, California June 12, 2006 -- IP Cores, Inc., setting the benchmark for security IP cores, today announced two silicon IP cores supporting new industry standards. New GLM1 and GLM2 IP cores enable System on Chip (SoC) vendors to build compact processors that support the AES/LRW and AES/GCM cryptographic algorithms.
"Addition of the combo IP cores to our portfolio continues our tradition of providing high value to SoC vendors by offering small-size, high-performance cores at low acquisition cost," said Dmitri Varsanofiev, CTO of IP Cores. "Our IP customers convert the small area requirements of our cores into a competitive advantage for their chips."
High-speed Encryption Protects Data in Storage and inside the Network
Advanced Encryption Standard (AES) is used to provide data security in storage, for example on a hard drive or tape, or on the network. Addressing the market demand for integrated high-speed AES crypto solutions for these two markets, IP Cores' GLM1 and GLM2 implement the AES/LRW and AES/GCM modes in a single core. GLM1 and GLM2 support 128-bit and 256-bit keys for design flexibility. GLM1 is designed for throughput of 12.8 Mbits per MHz, GLM2 delivers 25.6 Mbits per MHz.
AES/LRW cipher is used in the IEEE standard P1619 for hard disk encryption and P1619.1 for tape encryption. Both GLM1 and GLM2 in addition to AES/LRW also include the AES/GCM cipher designed to provide data security and authentication. AES/GCM allows parallelizable authentication implementations and therefore can be used for communication channels that require very high-speed authenticated encryption, such as supporting IEEE 802.1AE security for Ethernet networks, or IPsec RFC 4106. GLM1 and GLM2 configurations support AES/GCM and AES/LRW authenticated encryption throughput up to 10 Gbps in a single core using 130 nm process, with easy parallelization. Gate count for a fully self-contained GLM1 starts at 30K gates.
GLM1 and GLM2 contribute to the IP Cores' efficient portfolio of AES-based security IP cores. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores' product line, please visit www.ipcores.com.
About IP Cores, Inc.
IP Cores is a fast-moving company in the field of security IP cores. Founded 2 years ago, the company provides IP cores to protect communications and intellectual property.
