Serializer/Deserializer IP supports multiple protocols.

Press Release Summary:

Suited for high-speed processors and consumer electronics devices in high-definition TVs, set top boxes, and game consoles, 40 nm SerDes supports more than 100 lanes, from 1-12.5 Gb/lane on single IC with 5 mW/Gbps/lane power consumption. Unit is validated in over 30 industry standard protocols, including PCI Express, SATA, XAUI, XFI, and SGMII. Programmable features allow designers to use licensable IP to create differentiated SoC products while minimizing design risk.

Original Press Release:

Analog Bits Unveils Industry's Lowest Power 40nm High Bandwidth SerDes

5mw/Gb/s performance empowers multi-protocol multi-lane SoC

MOUNTAIN VIEW, Calif., -- Analog Bits, the Integrated Clocking and Interface IP leader, today announced the commercial availability of the industry's lowest power 40nm, high-speed Serializer/Deserializer (SerDes) IP. The breakthrough macro is programmable to support multiple protocols and small enough to be used in embedded SoCs.

The Analog Bits 40nm SerDes supports more than 100 lanes, from 1 to 12.5 Gb per lane, on single IC with a mere 5mw per gigabit per second per lane power consumption. It is currently in production in multiple applications and is validated in over 30 industry standard protocols including PCI Express, SATA, XAUI, XFI, SGMII, and delivers the lowest chip-to-chip communications latency.

"The new 40nm SerDes is ideal for high speed processors and consumer electronics devices in high definition TVs, set top boxes and game consoles. The IP's programmable features allow designers to use licensable IP to create highly differentiated SoC products while reducing design risk and speeding time-to-market," explains Mahesh Tirupattur, Executive Vice President, Analog Bits.

The Path to the Future

SerDes technology converts between parallel and serial communications protocols and is of increasing importance in embedded SoC applications.

"SerDes interfaces are becoming the norm across the SoC market," according to Rich Wawrzyniak, a Senior Market Analyst with Semico Research. Over the next several years, we project that more and more IP Subsystems will appear featuring SerDes interfaces to move data quickly to other on-chip subsystems and for high speed communications to the outside world. This will be especially true in applications that need to move large amounts of data at high speeds - like the spread of HD Video capability into portable consumer devices." A recent Semico Research report forecasts growth trends of IP Subsystems into the SoC market and is available from

Analog Bits new SerDes Interconnect is tested and currently available down to 40nm process geometries, with other nodes to follow. For information about Analog Bits' IP latest products, please visit

About Analog Bits: Founded in 1995, Analog Bits, Inc. is the leading supplier of integrated timing and interconnect IP. Products include precision clocking macros such as PLL's & DLL's, programmable interconnects such as multi-protocol SerDes/PMA and programmable I/O's as well as specialized memories such as high-speed SRAMs and T-CAMs. With billions IP fabricated in customer silicon from 0.35-micron to 28-nanometer processes, Analog Bits has the heritage of "first time working silicon" at merchant foundries and IDMs. For more information visit

CONTACT: Mahesh Tirupattur of Analog Bits, Inc., +1-650-314-0200, [email protected]

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