PHY targets Ethernet Passive Optical Network applications.
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Press Release Summary:
Designed to meet IEEE802.3av standard, OLT SerDes PHY enables symmetrical operation at 10.3125 Gbps for downstream and upstream links. Built-in burst-mode BIST allows CDR to recover data bursts in less than 50 ns, even in high jitter. Unit's serial input port utilizes multivoltage-compatible CML interface, allowing it to be directly coupled to PMD device supporting interfaces from 0.5-3.3 V. It also has parallel ports, with 17-bit transmit/receive interface, that operate at 644 Mbps.
Original Press Release:
K-micro Unveils OLT SerDes PHY for 10GEPON Applications
New PHY to meet emerging IEEE802.3av standard developed by 10GEPON task force, enabling symmetrical operation at 10.3125 Gbps data for downstream and upstream links
SAN JOSE, Calif., May 11 / / - K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced ASICs, announced a unique OLT SerDes PHY for 10 Gbps Ethernet Passive Optical Network (10GEPON) applications. Targeted to meet the emerging IEEE802.3av standard developed by the 10GEPON task force, the new PHY enables symmetrical operation at 10.3125 Gbps data for the downstream and upstream links.
"We are proud to be bringing a robust product for the 10GEPON market that meets the sub 50 ns lock time challenge, enabling development of OLT solutions without putting excessive demands on PMD devices," said Vijay Pathak, CTO at K-micro. "Co-existence compatibility is retained by providing a by-pass connection to an external 1.25 Gbps SerDes PHY for ONU applications. SerDes IP will be available for ASIC integration in mid 2010 in 65 nm technology."
Using its comprehensive built-in burst-mode BIST, the CDR for this new PHY is shown to recover data bursts in less than 50 ns even in the presence of high jitter specified in draft standard (0.76 UI @BER= 1E-3). The serial input port of this device employs a multi-voltage compatible CML interface, allowing it to be directly coupled to the PMD device supporting any CML interface ranging between 0.5V to 3.3V. This eliminates the need for an AC coupling capacitor whose long settling time would have added overhead to the system. Parallel ports of this PHY employ 17 bit transmit and receive interface designed around OIF's SFI-4.1 specifications and operate at 644 Mbps.
In general, when data input jitter is high, faster clock recovery is associated with higher jitter in the recovered clock thus degrading the BER and making it difficult to implement FEC function. This conflict is resolved by careful control of burst mode period and CDR design optimization. Registration with a new ONU can be achieved within 400 ns without complex controls from MAC layer. "These features make the PHY 'user friendly' and facilitate easier system integration," added Pathak.
About K-micro (Kawasaki Microelectronics America, Inc.)
K-micro's innovative ASIC technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking and storage markets. The company is an active participant in industry standards organizations, including InterNational Committee for Information Technology Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, PCI Special Interest Group (PCI-SIG), USB Implementers Forum, Universal Plug and Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline Networking Alliance (HomePNA), International Telecommunication Union (ITU) and OCP International Partnership (OCP-IP). K-micro has design centers in San Jose, Taipei, and Tokyo. For more information, contact the company at 408-570-0555, or visit http://www.k-micro.us/
Source: K-micro
Web Site: http://www.k-micro.us/
