Press Release Summary:
Leveraging EDC (electronic dispersion compensation) technology, AEL2000 series single- and multi-channel LAN PHY devices combine PHY/SerDes technology with fully compliant IEEE 802.3aq 10GBASE-LRM EDC engine. Devices include 10G transmit pre-emphasis and support for SGMII modes to facilitate backward compatibility with 1 GbE SFP applications. They also feature integrated PRBS and packet-level test pattern generators and checkers for device built-in self test functions.
Original Press Release:
Aeluros Announces New Family of Multi-Channel 10G PHY Devices
Industry's Leading Multi-Channel 10G PHY Devices Will Target High-Density SFP+ Applications
MOUNTAIN VIEW, Calif., March 1 -- Aeluros, the leading supplier of low-power CMOS-based 10G PHY solutions, today announced the AEL2000 product family of single and multi-channel PHY devices targeted for 10GbE SFP+ applications. Leveraging the success of its integrated EDC technology announced last year, and the robust, low-power 10G PHY/SerDes devices that it is known for, Aeluros is announcing its family of EDC-rich PHY devices to address exactly this SFP+ market need. As the EDC (electronic dispersion compensation) function migrates out of the 10G optical modules onto system line-cards with SFP+ applications, the stage is set for a new set of IC vendors to fill the need with low-power, high performance 10G PHY devices.
About the AEL2000 PHY/SerDes
The AEL2000 family of SFP+ PHY/SerDes includes single, and multi-channel LAN PHY devices that combine Aeluros' existing industry-leading low-power PHY/SerDes technology with its fully compliant IEEE 802.3aq 10GBASE-LRM EDC engine. Additionally, the devices include 10G transmit pre-emphasis and support for special SGMII modes to facilitate backward compatibility with 1GbE SFP applications. They also feature integrated PRBS and packet-level test pattern generators and checkers for effective device built-in self test (BIST) functions. The AEL2000 family of SFP+ PHYs is designed to address all the emerging system architectures. This includes the:
oAEL2003 -- a single channel SFI/XFI PHY with EDC (compliant with both 10GBASE-LRM and SFP+ MSA)
oAEL2005 -- a single channel SFI/XAUI PHY with EDC (compliant with both 10GBASE-LRM and SFP+ MSA)
oAEL2006 -- a dual channel SFI/XFI PHY with EDC (compliant with both 10GBASE-LRM and SFP+ MSA)
oAEL2010 -- a dual channel SFI/XAUI PHY with EDC (compliant with both 10GBASE-LRM and SFP+ MSA)
The AEL2003 and AEL2005 have already been sampling to various customers.
Interoperability testing has also been performed with SFP+ modules from 5 different modules vendors. To allow system designers to use a single solution for all reaches, the devices provide added flexibility by interoperating with:
oLinear SFP+ modules
oLimiting SFP+ modules
All the devices maintain the low power features and optimized cost structure made possible by generic CMOS process technology, plastic BGA or QLP packaging and expert design techniques.
"We are very excited to launch the AEL2000 family of multi-channel SFP+ 10GbE PHY devices," said Shantanu Mitra, Vice President of Marketing & Sales at Aeluros. "With the launch of these products Aeluros is well-positioned to lead the transition to high density 10GbE SFP+ based servers and switches in data centers. The small design footprint of these devices along with the programmability and robustness of the EDC engine will allow system designers to build dense and compact line cards quickly, while dynamically accounting for any variations in board manufacturing processes or other time varying behavior."
About Aeluros's EDC Technology
The core of the AEL2000 family of 10G PHY devices is Aeluros's industry-leading low-power CMOS EDC Engine for 10GBASE-LRM applications. This EDC engine was first demonstrated at OFC|NFOEC 2006 in the AEL1003 single channel XAUI PHY device for X2-LRM applications. The extensive experience acquired through rigorous testing of the Aeluros EDC engine in X2-LRM applications, has now been proliferated to the AEL2000 family. Aeluros's CMOS EDC engine is compliant with the 10GBASE-LRM (802.3aq) stress pulses including additional FR4 traces emulating worst case SFI channel loss. Receiver sensitivity, as measured using industry-standard 10GBASE-LRM test systems, shows excellent margin over the 6.5dbm specification limits -- at both room temperature and 75 degrees C.
Aeluros's EDC engine was also demonstrated at an industry-wide LRM interoperability test conducted in September 2006. The EDC technology will also be shown in booth #2877 at the upcoming OFC|NFOEC tradeshow in Anaheim, CA from March 27th to 29th, 2007.
Aeluros, Inc. is a fabless semiconductor company innovating serial, high-performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. For more information about Aeluros, please visit the company's web site at www.aeluros.com .