Open Pin Field Arrays deliver high-speed performance.

Press Release Summary:

High-density LP Array™ (LPAM and LPAF Series) supports high-speed applications that require reliable, high-pin count solutions in low-profile design. Available in 4, 4.5, and 5 mm mated heights with up to 180 total pins in 4 or 6 row configurations, arrays feature dual wipe contact system on 1.27 x 1.27 mm pitch grid for maximum grounding and routing flexibility. Lead-free solder crimp terminations facilitate processing, and tin-lead solder crimp is also available.

Original Press Release:

Samtec's New LP Array(TM) Delivers High Speed Performance with Low Profile Stack Heights

Samtec’s LP Array™ (LPAM and LPAF Series) supports high speed applications that require reliable, high pin count solutions in a low profile design. This most recent addition to Samtec’s line of high density, open pin field arrays is available in 4 mm, 4,5 mm and 5 mm mated heights with up to 180 total pins in four or six row configurations. Higher pin count versions are in development.

LP Array™ high speed, low profile arrays feature a dual wipe contact system on a .050” (1,27 mm) x  .050” (1,27 mm) pitch grid for maximum grounding and routing flexibility. Standard lead-free solder crimp terminations allow for ease of processing. Tin-lead solder crimp is also available. Optional pick and place pads are available for automated placement on the PCB. Other pin counts, row counts and gold plating options are also available for additional design flexibility.

Samtec’s full line of high speed, high density products includes SEARAY™ Open Pin Field Arrays which feature Edge Rate™ contacts optimized for signal integrity. The .050" (1,27 mm)  pitch system is available with up to 500 I/Os in stack heights from 7 mm to 40 mm. Right angle for micro backplane applications and press fit tail options provide greater system flexibility. A 0,80 mm  (.0347”) pitch system offers up to a 50 percent board space savings with 7 mm and 10 mm stack heights. In addition, DP Array® Differential Pair Arrays provide perimeter grounds and staggered pin layout to eliminate interstitial grounds and make board routing easier with performance up to 1 terabit per connector.

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