Microarchitecture lays foundation for synthesizable cores.

Press Release Summary:



MIPS32(TM) 24K(TM) provides single issue, 8-stage pipeline; hardware-based cache coherency to support multi-processor scaling; configurable memory management unit with TLB or fixed mapping; and 64-bit memory subsystem with up to 6 read transactions. Cores based on microarchitecture offer 400-500 MHz performance in 0.13 µm process.



Original Press Release:



New Microarchitecture from MIPS Technologies



A license to innovate

From its inception over 20 years ago, the MIPS(R) architecture has represented innovation and performance. Today, MIPS Technologies and its licensees continue to lead in system-performance and innovative solutions for established and emerging markets. With over 16 design teams actively developing the architecture, hundreds of successful implementations throughout the world, and a vibrant ecosystem of third party tools and software --MIPS continues to be at the core of the user experience.

This week, MIPS Technologies is pleased to introduce the MIPS32(tm) 24K(tm) microarchitecture, another marker of innovation and performance. The 24K(tm) microarchitecture lays the foundation for MIPS Technologies' next family of high-performance, synthesizable cores. In fact, with an operating performance range of 400 to 550 MHZ (worst case) in 0.13um processes, cores based on the 24K will be the highest-performance, synthesizable cores available for licensing. The high-performance and programmable features of the 24K microarchitecture address the changing economics of SOC design and help engineers increase profitability by extending their product's lifecycle.

Other outstanding attributes of the 24K microarchitecture include:
o Single issue, 8-stage pipeline
o Architected for scalability beyond 0.13mm technology nodes
o Hardware-based cache coherency to support multi-processor scaling
o Configurable memory management unit with TLB or fixed mapping
o 64-bit high performance memory subsystem with up to six outstanding read transactions

Global examples of innovation with the MIPS architecture abound. From Hsinchu to Herzilya, Munich and Mountain View, MIPS Technologies' and its licensees have driven the MIPS architecture into a vast and diverse range of embedded applications. In the Summer 2003 issue of the Pipeline(tm) newsletter, explore how some of these MIPS-based(tm) design wins and solutions are putting MIPS at the core of the user experience.

For additional details about the MIPS32 24K microarchitecture and to read the Summer 2003 edition of the Pipeline in its entirety, please go to www.mips.com.

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