SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it plans to exhibit its latest Design for Manufacturing (DFM) Physical Signoff and Computational Lithography technologies at this year's SPIE Advanced Lithography Exhibition at booth 227 from February 22 to 26, 2015, in San Jose, CA.
To register for the conference, visit http://www.cadence.com/news/spie.
The following technologies are scheduled for demonstrations at the exhibition:
-- Cadence® Process and Proximity Correction
-- Cadence physical and electrical DFM solutions
-- Cadence Virtuoso® Integrated Physical Verification System
Cadence is also scheduled to deliver several speaking sessions to discuss new developments in these technologies and how they can help solve today's process verification challenges. The scheduled speaking sessions include:
Layout dependent effects analysis on SMIC 28nm process (Paper 9427-14)
February 25, 2015, from 2:50 - 3:10pm
Design layout analysis and DFM optimization using topological patterns (Paper 9427-26)
February 26, 2015, from 4:10 - 4:30pm
Automation for pattern library creation and in-design optimization (Paper 9427-27)
February 26, 2015, from 4:30 - 4:50pm
For more detail on the speaker sessions, please visit
February 22 to 26, 2015
Booth 227 at SPIE Advanced Lithography Exhibition
San Jose Marriott and San Jose Convention Center
San Jose, California
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com/.
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Web Site: http://www.cadence.com