SAN JOSE, Calif. — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it is scheduled to demonstrate 16-nanometer (nm) FinFET Plus (16FF+) and 10nm advanced-node technologies that optimize customer designs and manufacturing efficiency at this year's TSMC 2015 Technology Symposium at booth 103 on April 7, 2015, in San Jose, Calif.
Cadence is planning to hold several demonstrations across a broad range of technology solutions including:
Custom and Mixed-Signal Design
-- Virtuoso® Liberate™ library characterization solution,
highlighting 10nm requirements and methodologies
-- Spectre® simulation platform for analog and mixed-signal verification
-- Avoiding density gradient effects in 16FF+ designs with Virtuoso
-- Virtuoso Layout Suite for Electrically Aware Design for real-time
Digital Design and Signoff
-- Certified digital implementation flow for TSMC 16FF+
-- Comprehensive, foundry-qualified signoff portfolio for FinFET
Intellectual Property (IP)
-- Low-latency, silicon-proven DDR/LPDDR IP
-- Low-energy face detection with Tensilica® IP
-- Stratus™ High-Level Synthesis and the Cadence® System
WHEN: April 7, 2015
WHERE: Booth 103
TSMC 2015 Technology Symposium
San Jose McEnery Convention Center
150 West San Carlos Street
San Jose, CA 95113
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at http://www.cadence.com/.
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Spectre, Tensilica, Virtuoso and the Cadence logo are registered trademarks and Liberate and Stratus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com