Press Release Summary:
Focused on advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs, IC packaging design and analysis solution includes CadenceÂ® OrbitIO™ Interconnect Designer, Cadence System-in-Package (SiP) Layout, and Cadence Physical Verification System (PVS). Capabilities enable multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.
Original Press Release:
Cadence Announces Availability of Complete IC Packaging Design and Analysis Solutions for Advanced Fan-Out Wafer-Level Chip Scale Packaging
Cross-fabric optimization accelerates multi-chip integration for smaller, lighter, power-optimized wireless mobile devices
SAN JOSE, Calif. – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the industry's only foundry-proven IC packaging design and analysis solutions for advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The new capabilities enable the faster multi-chip integration that is ideal for smaller, lighter and power-optimized wireless mobile devices.
This complete IC packaging design and analysis solution includes the Cadence® OrbitIO™ Interconnect Designer, Cadence System-in-Package (SiP) Layout and Cadence Physical Verification System (PVS). This set of offerings enables multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.
The new Cadence SiP Layout WLCSP option integrated with PVS provides generic silicon wafer-based packaging methodologies previously validated by TSMC for their Integrated Fan-Out (InFO) process. Enhancements to OrbitIO Interconnect Designer strengthen 2.5D interposer package design support, providing optimal multi-die, single package interconnect integration. This enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance. For more information on the Cadence IC packaging design and analysis solution, visit http://www.cadence.com/news/ICpackaging172.
"Wireless mobility and wireless-enabled is the trend at all levels of electronic-centric products, from smartphones to cars to home appliances and beyond. They all need thin, lightweight, low-power yet high-performance devices at their core. This is the sweet spot for WLCSP, fueling its predicted explosion in adoption," said Steve Durrill, senior product engineering group director for the PCB Group at Cadence. "Our latest release enables broad WLCSP-enabled design and foundry and OSAT manufacturing signoff, which in turn helps fabless semiconductor and systems companies deliver ultra-thin mobile-focused devices using the latest foundry and OSAT IC package manufacturing approaches."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and OrbitIO is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
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