Press Release Summary:
Fully compliant with ITU-G.813 and Telcordia GR1244 and GR253, Model STC5230 offers single chip solution for timing source in SDH, SONET, and Synchronous Ethernet network elements. It accepts 12 reference inputs and generates 9 independent synchronized output clocks, and offers 2 independent timing generators, T0 and T4, for Synchronous Equipment Timing Source (SETS). Available in TQ100 package, device operates with external OCXO or TCXO as its MCLK at 20 MHz.
Original Press Release:
Connor-Winfield's New STC5230 Is a Single Chip Synchronous Clock Solution for SETS
Aurora, IL - The STC5230 is a single chip solution of timing source in SDH, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-G.813 and Telcordia GR1244 and GR253.
The STC5230 accepts 12 reference inputs and generates 9 independent synchronized output clocks. Reference input frequencies are automatically detected, and inputs are individually monitored for quality. Active reference selection may be manual or automatic. All reference switches are hitless. Synchronized outputs may be programmed for a wide variety of SONET and SDH as well as Synchronous Ethernet frequencies.
Two independent timing generators, T0 and T4, provide the essential functions for Synchronous Equipment Timing Source (SETS). Each timing generator includes a DPLL (Digital Phase-Locked Loop), which may operate in the Freerun, Synchronized, and Holdover modes. Both timing generators support master/slave operation for redundant applications. The proprietary SyncLink(TM) cross-couple data link provides master/slave phase information and state data to ensure seamless side switches.
A standard SPI serial bus interface provides access to the STC5230's comprehensive, yet simple to use internal control and status registers. The device operates with an external OCXO or TCXO as its MCLK at 20 MHz.
The STC5230 is capable of field upgrade with optional external EEPROM or via the bus interface.
o For SDH SETS, SONET Stratum 3, 4E, 4 and SMC, and Synchronous Ethernet
o Two timing generators, T0 and T4, for SETS
o Complies with ITU-G.813, Telcordia GR1244, and GR253
o Supports Master/Slave redundant application with the SyncLink(TM) cross-couple data links
o Accepts 12 individual clock reference inputs
o Reference clock inputs are automatically frequency detected; each is monitored for quality
o Supports manual and automatic reference selection
o T0 and T4 have independent reference lists and priority tables for automatic reference selection
o Output 9 synchronized clocks
o Could compensate the phase delay of the cross-couple links, in 0.1ns steps up to 409.5ns
o Capable to trace the round-trip phase delay of the master/slave cross-couple links
o Hit-less reference and master/slave switching
o Phase rebuild on re-lock and reference switches
o Programmable loop bandwidth of each DPLL of the T0 and T4 timing generator, from 90 mHz to 107Hz
o Supports SPI bus interface
o Field upgrade capability
o IEEE 1149.1 JTAG boundary scan
o Available in TQ100 package
For more information contact:
The Connor-Winfield Corporation
The Connor-Winfield Corporation
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722 I Fax: 630-851-5040
Contact: Ray Kepka
630.851.4722 x 4224