I/O Card supports data rates up to 50 MHz.
Press Release Summary:
GC5050 high-speed dynamic digital I/O card has built-in Algorithmic Sequencer that plugs into any PCI slot and allows users to create loops and branches to manipulate output vectors. It provides real-time digital stimulus and capture with 32 pins per card. Up to 16 cards may be daisy-chained for total of 512 pins. Memory behind each pin is configurable from 256 Kbit to 1 Mbit and is user upgradeable. Clock rates are programmable from 750 Hz to 50 MHz.Original Press Release:
GC5050 Digital I/O
GC5050 DIGITAL I/O
DYNAMIC DIGITAL I/O
- 32 bi-directional I/0 pins
- Sixteen cards may be daisy-chained for a total of 512 pins using the same timing set
- 256 Kbit to 1 Mbit memory behind each pin
- Programmable clock rates from 750 Hz to 50 MHz
- Sequencer allows conditional branches, loops, and subroutines
- Advanced features for UUT synchronizahon
- Multiple I/O options include TTL, PECL, LVDS, and Programmable levels
- Graphical programming of sequencer and vector generation
- PCI-Bus architecture provides for fast loading and readback of test vectors
FEATURES
The GC5050 is a high-speed dynamic digital I/O card with a built-in Algorithmic Sequencer that plugs into any PCI slot. Based on
Geotest's award-wining GT50-DIO, the GC5050 provides all the features of high-speed dynamic digital testers normally seen only in large functional test systems. The GC5050 may be combined with other PC instruments to form a mixed-signal test
system.
APPLICATIONS
- Automatic Test Equipment (ATE)
- High speed functional digital test
- Digital pattern generator
- Vector capture
- Hybrid and digital device test
- Memory testing
- Event sequencer, logic pattern capture
ARCHITECTURE
The GC5050 provides real-time digital stimulus and capture with 32 pins per card. Up to 16 cards can be daisy-chained for a total of up to 512 pins. The GC5050 supports data rates up to 50 MHz (60 MHz optional). The 32 pins can be configured as input or
output in groups of eight. The direction of each group may be changed dynamically within the sequencer, externally, or both.
Clock and strobe signals are distributed to the cards via a daisy-chained ribbon cable. These signals can be generated internally or externally. The external control signals allow full synchronization with the unit under test (UUT) and minimize the initialization part of the test. The algorithmic sequencer allows users to create loops and branches to manipulate the output vectors. All of the sequencer commands can be conditioned
using the external event bus. This gives the GC5050 card the capability to generate test vectors indefinitely at maximum test rates. Internal and external trigger and pause commands are available in several modes.
The memory behind each pin is configurable from 256 Kbit to 1 Mbit (2Mbit and 4Mbit optional) and is user upgradeable. Separate memories are provided for output data, response data, and test step sequencing commands. The separate memory for response data lets the application read the activity on the UUT pins independent of the bi-directional mode. This is an important
feature lacking in most high-speed digital I/O applications.
I/0 ARCHITECTURE
The GC5050 requires a plug-in module for its I/O stage; these plug-in modules are called I/O modules and must be specified at the time the GC5050 is ordered. Geotest offers various I/O modules with input and output levels that meet the requirement of any digital test application. These include: TTL, PECL, LVDS
and Programmable levels.
The TTL I/O Module provides 32 TTL channels compatible with both 5V and 3.3V logic.
The PECL I/O modules provide 32 differential PECL channels compatible with Positive ECL levels.
The LVDS I/O module provides 32 differential LVDS channels compatible with LVDS levels.
The Programmable levels I/O module provides 32 channels. The output of the channels and the input threshold can be programmable in groups of 16 channels from 0.3V to 9V. This I/O module can drive channels up to l00mA per channel or 160mA per each group of 8 channels. Additional custom I/O modules, such as
differential TTL, are also available. Consult factory for details.
CONFIGURATION
The I/O Module is mounted on the GC5050. I/O module type and memory size must be specified at the time the GC5050 is ordered.
The GC5050 requires 3 memory modules (Input, Output, and Control). The GC5050 supports both 256K- and 1 M-memory module and optional support for 2M and 4M modules.
The GC5050 may be configured as a Master or as a Slave. The Master provides the timing signals to up to 15 additional Slaves.
PROGRAMMING
The GC5050 is provided with libraries to use with Windows (DLL) or DOS-based applications. This allows the GC5050 to be used with programming languages such as ATEasy, C, C++, Basic, and Pascal. Examples are provided in C using the MS-Windows Dynamic Link Library (DLL) and MS-DOS libraries. A virtual front panel
allows the user to operate the GC5050 as a standalone instrument (see Figure 1). Vector generation and programming of the GC5050 can also be accomplished with Geotest's DIOEasy software.
DIOEasy is a graphical environment that simplifies the task of vector generation and test sequence programming.
ATEasy provides the ideal software platform when integrating the GC5050 in an automated test system. ATEasy allows programmers and non-programmers alike to develop test related applications quickly and efficiently.
