Press Release Summary:
Built on UMC's 40 nm process using third-generation ASMBL(TM) architecture, Virtex-6 LX760 Devices comprise 3 domain-optimized FPGA platforms that help those who need raw logic density and optimized I/O performance get started on projects using ISEÂ® Design Suite v11.4. Features such as 1,200 SelectIO pins and 25,920 Kb Block RAM, which serve to meet system partitioning as well as data buffering requirements, suit applications requiring intensive computation and high logic density.
Original Press Release:
Industry's Biggest, Highest Performance FPGA Now Shipping from Xilinx
Delivery of Virtex-6 LX760 Devices Extends FPGA Logic Capacity by More Than 2x
SAN JOSE, Calif. -- Xilinx, Inc. (NASDAQ:XLNX) today announced the first shipments and availability of its Virtex®-6 LX760 device. As the industry's largest FPGA available for delivery with immediate design tool support, the Virtex-6 LX760 device enables Xilinx customers who need raw logic density and industry-leading I/O performance to get started on their projects today using the Xilinx ISE® Design Suite 11.4.
"The Virtex-6 LX760 device offers more than two and a half times the density of the largest Virtex-5 device, so it was a natural choice for us as we transition to our next generation Rapid Prototyping platforms," said Gary Meyers, vice president and general manager of the Synplicity Business Group at Synopsys. "Receiving the first delivery of the LX760 devices accelerates our development and helps ensure that our customers receive the most advanced prototyping platforms at the earliest possible time."
The Virtex-6 LX760 device is ideal for any application that requires intensive computational performance and high logic density. For example, the new large-capacity device enables designers to use a single-FPGA to prototype or emulate a greater range of ASIC designs than ever before. In addition to high logic capacity, the LX760 device offers a higher I/O count than competing FPGAs to simplify the challenge of partitioning a large ASIC netlist across multiple FPGAs. Meanwhile, the ISE Design Suite version 11.4 reduces compile time by 30% to enable large, complex and highly utilized Virtex-6 designs as well as increased productivity through more design turns per day.
"Shipping the largest FPGA in the market demonstrates Xilinx's ability to deliver leading edge architectures at the 40nm process technology node," said Xilinx Senior Director of Marketing Patrick Dorsey. "As the industry's leading FPGA product, each succeeding family of Virtex FPGAs enables our customers to more rapidly bring new applications to market by delivering new levels of capacity and performance."
The Virtex-6 LX760 device leads the industry in its I/O count and embedded memory with 1,200 SelectIO pins and 25,920Kbits Block RAM to meet system partitioning as well as data buffering requirements. In order to serve the needs of applications requiring the highest logic and embedded memory requirements, the LX760 device is optimized to tradeoff high-speed serial transceivers for higher I/O, logic, and embedded memory capacity.
About the Virtex-6 Family
Built on UMC's 40nm process using third-generation Xilinx ASMBL(TM) architecture, the Virtex-6 FPGA family is supported by a new generation of development tools and a vast library of IP already available for the Virtex-5 FPGA family to ensure productive development and design migration. Providing 15% higher performance and 50% lower system power consumption compared to competitive 40nm FPGA offerings, the new devices operate on a 1.0v core voltage with an available 0.9v low-power option. The Virtex-6 FPGA family comprises three domain-optimized FPGA platforms that deliver different feature mixes to best address a variety of customer applications:
-- Virtex-6 LXT FPGAs - optimized for applications that require high-performance logic, DSP and serial connectivity with low-power GTX 6.5Gb/s serial transceivers
-- Virtex-6 SXT FPGAs - optimized for applications that require ultra high-performance DSP and serial connectivity with low-power GTX 6.5Gb/s serial transceivers
-- Virtex-6 HXT FPGAs - optimized for communications applications that require the highest-speed serial connectivity with up to 64 serial transceivers supporting up to 11.2Gb/s
Along with the 45nm Spartan®-6 family, the Virtex-6 family makes up the silicon base of Xilinx Targeted Design Platforms that significantly shorten the time it takes to reach optimal levels of system performance, while ensuring low levels of power consumption, during system-on-chip (SoC) development using the ISE Design Suite; third-party synthesis, simulation, and signal integrity tools; reference designs; and IP. Development kits supporting both families are available now. Visit xilinx.com/kits to learn more.
Pricing and Availability
Initial Virtex-6 LX760 samples are shipping today and customers can start their designs immediately by downloading a free evaluation of the ISE® Design Suite version 11.4. Please visit www.xilinx.com/ise_eval/index.htm. Detailed pricing information for Virtex-6 FPGAs is available through Xilinx sales offices and distributors. Xilinx EasyPath(TM)-6 FPGAs offer the industry's lowest total cost with the lowest-risk from high-performance FPGA to production ready devices in just six weeks, the fastest turnaround time of any FPGA cost reduction solution. For more information, please visit xilinx.com/virtex6.
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.
XILINX, the Xilinx Logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.