FPGA Cores enable manipulation of signal sample rate.
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Press Release Summary:
Featuring scalable architecture, Fractional Resampling Cores can be used to perform up-sampling or down-sampling of high-speed digital signals. Units support resampling of one channel or thousands of channels simultaneously. Core for Xilinx Virtex II Pro 50 FPGA is able to down-sample 512 channels simultaneously and independently. It supports max input channel sample rates up to 25 MS/s and max aggregate sample rate for all channels combined of up to 280 MS/s.
Original Press Release:
New, Unique Fractional Resampling Cores From RF Engines
New FPGA cores achieve industry leading performance and flexibility, and major system cost reductions
Issued: 8 June 2005
RF Engines Ltd (RFEL), the specialists in innovative signal processing design, has developed a new range of Fractional Resampling Architectures for FPGA that can be used to perform up-sampling or down-sampling of high-speed digital signals. The designs are based on a unique architecture that offers significantly greater user flexibility in the design of the resampling filter and better dynamic range, when compared to designs based on traditional architectures. The design is also unrivalled in its ability to efficiently handle thousands of channels simultaneously and independently.
Fractional resampling is a signal processing function that enables the manipulation of the signal sample rate, so that it may be precisely matched to the requirements of subsequent processing. This has many applications, but RF Engines designs are particularly relevant for matching symbol and sample rates in digital receivers, enabling the modulators and demodulators to be significantly simpler and cheaper. Examples include telecommunications modulators and demodulators, image and video processing, audio processing, and interfacing to hardware components with fixed sample rates.
John Summers, RF Engines' VP of Sales and Marketing commented, "These fractional resampler cores are the latest addition to our range of high performance signal processing building blocks. The new cores achieve industry leading performance and flexibility. They provide designers with much greater freedom in their system design and the ability to do all this with low risk and to a shortened timescale. In addition, and perhaps most importantly, they can help to achieve significantly reduced overall system design costs."
The RF Engines architecture is highly scalable, and has a unique benefit in that it can support resampling of just one channel or thousands of channels simultaneously, whilst maintaining efficient use of silicon resources, and providing excellent filtering performance in order to mitigate the effects of aliasing. The resampling rates can be selected with high precision, and allow selection of output sample rates with a resolution less than one Hertz. When operating on multiple input channels, the architectures treat each channel independently, allowing different input sampling rates, and rate changes for each channel. Furthermore, the rate change required for each channel can be updated at runtime, without affecting the operation of other channels.
The IP designs are provided as an EDIF netlist for either Xilinx or Altera FPGA devices, and are custom generated for each specific requirement to ensure a minimal FPGA footprint, and the lowest power consumption. As with all RF Engines cores, the Fractional Resamplers are supported by bit-true Matlab models, allowing early validation of the core through simulation, and thereby reducing risk.
An example core for the Xilinx Virtex II Pro 50 FPGA is able to down-sample 512 channels simultaneously and independently. The core supports maximum input channel sample rates up to 25 MS/s and a maximum aggregate sample rate for all channels combined of up to 280 MS/s. Each channel can be down sampled by a user-selectable factor of up to one hundred with a sub-Hertz frequency resolution. This particular core requires approximately 10% of the resources on the Pro 50.
RF Engines
RF Engines Limited (RFEL) is a UK based designer, providing high specification signal processing cores, system on chip designs, and FPGA based board solutions for applications in the defence, communications and instrumentation markets. These applications include base stations, wireless and wireline broadband communications systems, satellite communications systems, test and measurement instrumentation, as well as defence systems. More specifically, RFEL is a solutions provider for projects requiring complex front end, real time, wide and narrow band, flexible channelisation. RFEL provides a range of standard cores covering multiple FFT and unique PFT techniques, as well as system design services for specialist applications.
For further information, please see the website at www.rfel.com or contact RF Engines at Innovation Centre, St Cross Business Park, Newport, Isle of Wight, PO30 5WB, Great Britain. Tel +44 (0) 1983 550330. E-mail info@rfel.com
