Electrical DFM Solution aids chip analysis and optimization.

Press Release Summary:

Offered as complete and silicon correlated solution, OutPerform(TM) lets designers using sub-90 nm processes optimize and control impact of lithography, mask, etch, RET, OPC, and CMP effects on their chip parameters. It plugs directly into existing flows for cell design, IP, custom analog, and cell-based digital design. After identifying timing and leakage parametric hotspots for violations, solution produces timing optimization directives that drive place and route tools.

Original Press Release:

Clear Shape Announces OutPerform(TM) Electrical DFM Analysis and Optimization Solution

SANTA CLARA, Calif., Nov. 27 -- Clear Shape Technologies, Inc., a leader in variability-aware analysis and optimization solutions, today announced OutPerform, the first complete and silicon correlated electrical DFM analysis and optimization product to enable designers using sub-90 nm processes to optimize and control the impact of lithography, mask, etch, RET, OPC, and CMP effects on their chip parameters. OutPerform plugs directly into designer's existing flows for cell design, IP, custom analog and cell-based digital design.

OutPerform takes in the chip designers' timing and place and route data, along with encrypted fab technology files, and identifies timing and leakage parametric hotspots for violations due to systematic variations. It produces timing optimization directives that drive the place and route tools. OutPerform gets its silicon-accurate critical dimensions (CD) for devices and interconnects from Clear Shape's InShape(TM), which delivers accurate full-chip contour shape predictions across the process window in a matter of hours. Clear Shape's device and interconnect models for accurate prediction of silicon electrical behavior have already been validated in silicon at several semiconductor manufacturers.

"By using OutPerform in combination with InShape's model-based contour predictions, we were able to quickly and accurately do full-chip analysis of the electrical impact of systematic manufacturing variations on our chips," said Takaaki Kuwata, General Manager for the Advanced Device Development Division, Technology Foundation Development Operations Unit of NEC Electronics Corporation. "As a result, we were able to utilize our 90 nm process technology much more aggressively and have a closed-loop solution to address parametric issues associated with variability."

"UMC has collaborated with Clear Shape by using their OutPerform and InShape products to create DFM-aware libraries and IP for our customers designing at 65 nm and below," said Patrick Lin, Chief SOC Architect, System & Architecture Support at UMC. "Our goal is to provide our customers with the maximum benefit of our leading edge process technologies by providing variability-optimized building blocks. Due to the combined speed and accuracy of Clear Shape's model-based approach, we have been able to optimize our libraries and IP to account for the electrical impact of silicon contour variations."

"Variability in manufacturing is now creating barriers for chip designers to achieve entitled performance from highly capital intensive fabs," commented Atul Sharan. "Variability could turn out to be fatal or cost too much performance. The only way to effectively achieve entitled performance for your chip is to accurately determine the impact of these systematic variations by doing in-context parametric analysis utilizing certified technology files (i.e. optical prediction models) from the fab. The predictive analysis also needs to be fast in order to analyze large chips in hours."

Importance of Variability-Aware Electrical Design

At 90 nm and below, systematic variations are the greatest cause of chip failures, causing electrical issues such as timing, signal integrity and leakage power. For example, at 65 nanometers, systematic variations of 3nm on a transistor gate can cause a 20% variation in delay and have a 2x impact on leakage power.

With traditional corner-based design methodologies, margins are applied everywhere regardless of context. This over-design with excessive guardbanding stalls timing closure, and can still result in unexpected parametric failures due to unforeseen systematic manufacturing variations. Furthermore, over-designing to avoid DFM issues results in penalties to both area and leakage power.

With in-context model-based electrical DFM that incorporates fab technology information on lithography, RET, OPC, CMP, mask, and etch, chip designers can optimize their electrical parameters on-the-fly without any change to their library layout characterization, and tighten their design parameters knowing that the impact of variability has been carefully managed.

OutPerform Technology Foundation

o Full-chip optical effect computation based on model-based analysis from Clear Shape's flagship product -- InShape(TM).
o A new extraction paradigm to handle the data volume and accuracy required by this contour-based extraction demand.
o Silicon proven device modeling of contour-based (non-rectangular) transistor gates which takes into account the short channel effect of a MOSFET inside the device channel in order to extract the proper device parameters.
o Incremental, fast and accurate full-chip RC and device extraction based on the contour data generated from ideal shapes in GDSII.
o Incremental delay calculation based on the incremental RC and device parameters to identify timing violations.
o Full-chip leakage computation to detect power hot-spots.
o Physical design directives to optimize the layout to repair the timing hotspots.
o Standard interfaces that enable easy plug-in to the existing design flows.

OutPerform Fits in any Design Flow

OutPerform fits into existing place and route and layout design flows and provides a closed loop between design and manufacturing. Cell-based chip designers input their DEF, SPEF, library information, and fab DFM technology files into OutPerform. It is fast enough to quickly iterate with place and route: designers tighten their design margins, run place and route, then use OutPerform to identify hotspots and produce optimization directives. OutPerform also calculates the change in delay and timing skew based on the in-context shape variations and provides delay variations back to static timing analysis tools in the form of an incremental SDF. Therefore designers can verify and minimize the effects of variations on their cell-based design performance in their current design flow.

For custom design, OutPerform takes in a SPICE netlist and SPICE models and predicts current density across channels, extracting transistor parameters for transistors from the embedded InShape model-based silicon contour predictions. OutPerform then produces a back-annotated transistor SPICE netlist. It also applies the changes in RC data to the designer's existing DSPF or SPEF file to represent the true effects of in-context silicon shape variations, without creating new nodes or parasitic elements. Designers can then simulate the back-annotated transistor SPICE netlist with their SPICE simulator to check the effect of variations on their design and detect potential failures undetected by conventional tools and before going to silicon.

Pricing and Availability

Pricing starts at $300,000 per master license per year. OutPerform is available on Linux platforms. Distributed Processing is also available at incremental pricing.

About Clear Shape

Clear Shape Technologies, Inc. is focused on delivering a complete Variability Platform that allows designers to control and optimize the parametric and catastrophic impact of systematic manufacturing variations. Clear Shape's products are based on patent-pending technologies enabling designers to efficiently achieve entitled performance and yield. Clear Shape's flagship product InShape is in the DFM qualification program of all the major pure-play foundries and has been silicon-correlated at several IDMs. OutPerform, industry's first eDFM product has also been silicon validated. Clear Shape is backed by top-tier venture investors that include USVP, Intel Capital and KT Ventures (KLA Tencor). The company is headquartered at 3255-3 Scott Blvd, Suite 102 Santa Clara, Calif. 95054. For more information, visit www.clearshape.com/ or call +1 (408) 833-7130.

Clear Shape(TM) and OutPerform(TM) are registered trademarks of Clear Shape Technologies, Inc.

CONTACT: Gloria Nichols, Launch Marketing, +1-650-851-6919, gloria@launchm.com; Nitin Deo, Vice President, Marketing and Business Development, Clear Shape, +1-408-960-1578, nitin@clearshape.com

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