Dual Clock Translator IC supports wired network applications.
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Press Release Summary:
Addressing timing requirements of high-speed OTN de-mapping applications and high-density line cards, Model AD9559 simultaneously supports different frequencies for wired communications applications, including synchronous Ethernet, SONET/SDH, 1/10/100G Ethernet, and Fiber Channel. Quad-input programmable translator synchronously converts any standard input frequency to any standard output frequency at up to 1.25 GHz with sub-400-fs RMS total jitter over 12 kHz to 20 MHz integration bandwidth.
Original Press Release:
Dual Adaptive Clock Translator Supports Wide Range of Wired Network Applications Including OTN De-Mapping and High-Density Line Cards
NORWOOD, Mass.--Analog Devices, Inc. (ADI) today introduced a fully-programmable, jitter-attenuating, dual-clock translator IC (integrated circuit) to address the timing requirements of high-speed optical transport network (OTN) applications and high-density line cards. The AD9559 quad-input multiservice line card adaptive clock translator simultaneously supports different standard frequencies for wired communications applications, including synchronous Ethernet, SONET/SDH, 1/10/100G Ethernet, Fiber Channel, and other applications that require low jitter, flexibility and fast time-to-market. The AD9559 translator IC synchronously converts any standard input frequency to any standard output frequency at up to 1.25 GHz with sub-400-fs RMS (root mean square) total jitter over a 12-kHz to 20-MHz integration bandwidth. The AD9559 replaces two synchronous timing devices with a single IC, helping designers with board space constraints and cost optimization.
·Download data sheets and order samples: www.analog.com/AD9559
·For the single-channel version of this device, visit www.analog.com/AD9557
The AD9559 is the industry's most flexible high-performance dual adaptive clock translation solution for high-density line cards and OTN applications. Adaptive clocking allows the DPLL (digital PLL) divider ratios to be changed while the DPLL is locked. This enables the frequency at the output to be dynamically adjusted over a ± 100 ppm range, around the nominal output frequency, with a resolution in frequency step as low as sub-0.1 ppb, without breaking the loop and reprogramming the part. The AD9559 IC's parallel DPLL architecture allows the user to generate output clocks that are completely independent of each other. Each of the two DPLLs can be synchronized to one of up to four input references, and each DPLL generates two output clocks. The DPLL allows for reduction of input time jitter or phase noise associated with the external references.
The AD9559 continuously generates a clean (low jitter) valid output clock, even when all references have failed, by means of a digitally-controlled loop and holdover circuitry. The built-in programmability of the AD9559 clock translator allows network line card designers to use the same component in many different board designs, limiting the number of components needed and reducing overall system cost.
At 10 mm x 10 mm in size, the AD9559 clock translator provides a compact, frequency agile, cost effective clock for line card designers. Applications include data communications, next-generation wired networking applications, test and measurement, high-speed data acquisition, video applications, and wireless base station controllers.
Key Features of the AD9559 Quad-input Dual Adaptive Clock Translator
·Dual DPLL architecture, with four reference inputs (single-ended or differential) going to an input crosspoint
·Supports adaptive clocking and gapped clock input reference for OTN de-mapping applications
·Supports GR-1244 Stratum 3 stability in holdover mode
·Smooth reference switchover with virtually no disturbance on output phase.
·Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 Systems
·Supports ITU-T G.8262 Synchronous Ethernet slave clocks
·Supports ITU-T G.823, G.824, G.825, and G.8261
Availability, Pricing and Complementary Parts
| Product | Availability | Operating Temperature Range | Price each in 1,000 quantity | Packaging |
| AD9559 | Full Production | -40°C to 85°C | $19.26 | 10-mm x10-mm 72-lead LFCSP |
Complementary components include ADI's ADCLK9XX series of clock fanout buffers, including the ADCLK944, which achieves jitter performance of 25 fs (typical) over the integration bandwidth of 12 kHz to 20 MHz. For power management, the ADP150 or ADP222 ultralow noise, low dropout, linear regulators, or the ADP1829 dual PWM switching buck controller are recommended.
·For additional support, connect with engineers and ADI product experts on EngineerZone(TM), an online technical support community: ez.analog.com/community/clock_and_timing
About Analog Devices
Innovation, performance, and excellence are the cultural pillars on which Analog Devices has built one of the longest standing, highest growth companies within the technology sector. Acknowledged industry-wide as the world leader in data conversion and signal conditioning technology, Analog Devices serves over 60,000 customers, representing virtually all types of electronic equipment. Analog Devices is headquartered in Norwood, Massachusetts, with design and manufacturing facilities throughout the world. Analog Devices is included in the S&P 500 Index. www.analog.com.
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Contacts
Analog Devices, Inc.
Jim Surber, 336-605-4365
jim.surber@analog.com
